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order this document by MC68HC11FTS/d ?motorola inc., 1997 this document contains information on a new product. speci?ations and information herein are subject to change without notice. motorola semiconductor technical data m mc68hc11f1 mc68hc11fc0 technical summary 8-bit microcontroller 1 introduction the mc68hc11f1 is a high-performance member of the m68hc11 family of microcontroller units (mcus). high-speed expanded systems required the development of this chip with its extra input/output (i/o) ports, an increase in static ram (one kbyte), internal chip-select functions, and a non-multiplexed bus which reduces the need for external interface logic. the timer, serial i/o, and analog-to-digital (a/ d) converter enable functions similar to those found in the mc68hc11e9. the mc68hc11fc0 is a low cost, high-speed derivative of the mc68hc11f1. it does not have eeprom or an analog-to-digital converter. the mc68hc11fc0 can operate at bus speeds as high as six mhz. this document provides a brief overview of the structure, features, control registers, packaging infor- mation and availability of the mc68hc11f1 and mc68hc11fc0. for detailed information on m68hc11 subsystems, programming and the instruction set, refer to the m68hc11 reference manual (m68hc11rm/ad). 1.1 features ?mc68hc11 cpu ?512 bytes of on-chip electrically erasable programmable rom (eeprom) with block protect (mc68hc11f1 only) ?1024 bytes of on-chip ram (all saved during standby) ?enhanced 16-bit timer system ?3 input capture (ic) functions ?4 output compare (oc) functions ?4th ic or 5th oc (software selectable) ?on-board chip-selects with clock stretching ?real-time interrupt circuit ?8-bit pulse accumulator ?synchronous serial peripheral interface (spi) ?asynchronous nonreturn to zero (nrz) serial communication interface (sci) ?power saving stop and wait modes ?eight-channel 8-bit a/d converter (mc68hc11f1 only) ?computer operating properly (cop) watchdog system and clock monitor ?bus speeds of up to 6 mhz for the mc68hc11fc0 and up to 5 mhz for the mc68hc11f1 ?68-pin plcc (mc68hc11f1 only), 64-pin qfp (mc68hc11fc0 only), and 80-pin tqfp pack- age options
motorola mc68hc11f1/fc0 2 MC68HC11FTS/d 1.2 ordering information the following devices all have 1024 bytes of ram. in addition, the mc68hc11f1 devices have 512 bytes of eeprom. none of the devices contain on-chip rom. table 1 mc68hc11f1 standard device ordering information package temperature frequency mc order number 80-pin thin quad flat pack (tqfp) (14 mm x 14 mm, 1.4 mm thick) 0 to +70 5 mhz mc68hc11f1pu5 -40 to +85 c 2 mhz mc68hc11f1cpu2 3 mhz mc68hc11f1cpu3 4 mhz mc68hc11f1cpu4 5 mhz mc68hc11f1cpu5 ?40 to + 105 c 2 mhz mc68hc11f1vpu2 3 mhz mc68hc11f1vpu3 4 mhz mc68hc11f1vpu4 ?40 to + 125 c 2 mhz mc68hc11f1mpu2 3 mhz mc68hc11f1mpu3 4 mhz mc68hc11f1mpu4 68-pin plcc 0 to +70 5 mhz mc68hc11f1fn5 ?40 to + 85 c 2 mhz mc68hc11f1cfn2 3 mhz mc68hc11f1cfn3 4 mhz mc68hc11f1cfn4 5 mhz mc68hc11f1cfn5 ?40 to + 105 c 2 mhz mc68hc11f1vfn2 3 mhz mc68hc11f1vfn3 4 mhz mc68hc11f1vfn4 ?40 to + 125 c 2 mhz mc68hc11f1mfn2 3 mhz mc68hc11f1mfn3 4 mhz mc68hc11f1mfn4 table 2 mc68hc11f1 extended voltage (3.0 to 5.5 v) device ordering information package temperature frequency mc order number 68-pin plastic leaded chip carrier (plcc) 0 to +70 c 3 mhz mc68l11f1fn3 ?0 to +85 c 3 mhz mc68l11f1cfn3 80-pin thin quad flat pack (tqfp) 0 to +70 c 3 mhz mc68l11f1pu3 ?0 to +85 c 3 mhz mc68l11f1cpu3
mc68hc11f1/fc0 motorola MC68HC11FTS/d 3 table 3 mc68hc11fc0 standard device ordering information package temperature frequency mc order number 64-pin quad flat pack (qfp) ?0 to +85 c 4 mhz mc68hc11fc0cfu4 5 mhz mc68hc11fc0cfu5 0 to 70 c 6 mhz mc68hc11fc0fu6 80-pin thin quad flat pack (tqfp) ?0 to +85 c 4 mhz mc68hc11fc0cpu4 5 mhz mc68hc11fc0cpu5 0 to 70 c 6 mhz mc68hc11fc0pu6 table 4 mc68hc11fc0 extended voltage (3.0 to 5.5 v) device ordering information package temperature frequency mc order number 64-pin quad flat pack (qfp) ? to +70 c 3 mhz mc68l11fc0fu3 4 mhz mc68l11fc0fu4 80-pin thin quad flat pack (tqfp) 3 mhz mc68l11fc0pu3 4 mhz mc68l11fc0pu4
section page motorola mc68hc11f1/fc0 4 MC68HC11FTS/d 1 introduction 1 1.1 features ...................................................................................................................................... 1 1.2 ordering information ................................................................................................................... 2 1.3 block diagrams .......................................................................................................................... 6 2 pin assignments and signal descriptions 8 2.1 mc68hc11f1 pin assignments .................................................................................................. 8 2.2 mc68hc11fc0 pin assignments ............................................................................................. 10 2.3 pin descriptions ........................................................................................................................ 12 3 control registers 14 3.1 mc68hc11f1 control registers ............................................................................................... 14 3.2 mc68hc11fc0 control registers ............................................................................................ 16 4 operating modes and system initialization 18 4.1 operating modes ....................................................................................................................... 18 4.2 memory maps ............................................................................................................................ 19 4.3 system initialization registers .................................................................................................. 20 5 resets and interrupts 25 5.1 interrupt sources ....................................................................................................................... 25 5.2 reset and interrupt registers ................................................................................................... 26 6 electrically erasable programmable rom 29 6.1 eeprom operation .................................................................................................................. 29 6.2 eeprom registers ................................................................................................................... 29 6.3 eeprom programming and erasure ........................................................................................ 31 6.4 config register programming ............................................................................................... 32 7 parallel input/output 33 7.1 port a ........................................................................................................................................ 33 7.2 port b ........................................................................................................................................ 33 7.3 port c ........................................................................................................................................ 33 7.4 port d ........................................................................................................................................ 33 7.5 port e ........................................................................................................................................ 33 7.6 port f ......................................................................................................................................... 33 7.7 port g ........................................................................................................................................ 34 7.8 parallel i/o registers ................................................................................................................ 34 8 chip-selects 38 8.1 chip-select operation ............................................................................................................... 38 8.2 chip-select registers ................................................................................................................ 38 9 serial communications interface (sci) 42 9.1 sci block diagrams .................................................................................................................. 42 9.2 sci registers ............................................................................................................................ 44 10 serial peripheral interface 49 10.1 spi block diagram .................................................................................................................... 49 10.2 spi registers ............................................................................................................................ 50 11 analog-to-digital converter 53 11.1 input pins .................................................................................................................................. 54 11.2 conversion sequence ............................................................................................................... 54 11.3 a/d registers ............................................................................................................................ 55 12 main timer 57 12.1 timer operation ........................................................................................................................ 57 12.2 timer registers ......................................................................................................................... 59 13 pulse accumulator 64 13.1 pulse accumulator block diagram ............................................................................................ 64 13.2 pulse accumulator registers .................................................................................................... 64 table of contents
register address page mc68hc11f1/fc0 motorola MC68HC11FTS/d 5 adctl ................ a/d control/status .........................................................$1030 ..........................55 baud .................. baud rate......................................................................$102b ..........................44 bprot................ block protect..................................................................$1035 ..........................29 cforc ............... timer force compare....................................................$100b ..........................59 config .............. eeprom mapping, cop, eeprom enables ...............$103f ............. 24 , 28 , 30 coprst ............. arm/reset cop timer circuitry.....................................$103a ..........................27 csctl ................ chip-select control........................................................$105d ..........................39 csgadr............. general-purpose chip-select address register ........... $105e .........................40 csgsiz............... general-purpose chip-select size register ................$105f ..........................40 csstrh ............. clock stretching.............................................................$105c ..........................38 ddra .................. port a data register......................................................$1001 ..........................34 ddrc.................. data direction register for port c .................................$1007 ..........................35 ddrd.................. data direction register for port d .................................$1009 ..........................36 ddrg.................. data direction register for port g .................................$1003 ..........................35 hprio................. highest priority interrupt and miscellaneous ................$103c ................... 20 , 27 init ..................... ram and i/o mapping ...................................................$103d ................... 21 , 22 oc1d .................. output compare 1 data ................................................$100d ..........................59 oc1m.................. output compare 1 mask ...............................................$100c ..........................59 opt2................... system configuration option register 2 .......................$1038 ............. 22 , 36 , 52 option .............. system configuration options .......................................$1039 ............. 23 , 26 , 56 pacnt ................ pulse accumulator count ..............................................$1027 ..........................66 pactl................. pulse accumulator control ...........................................$1026 ................... 63 , 65 porta................ port a data ....................................................................$1000 ..........................34 portb................ port b data ....................................................................$1004 ..........................35 portc................ port c data ....................................................................$1006 ..........................35 portd................ port d data ....................................................................$1008 ..........................36 porte................ port e data ....................................................................$100a ..........................36 portf ................ port f data ....................................................................$1005 ..........................35 portg ............... port g data....................................................................$1002 ..........................34 pprog ............... eeprom programming control ....................................$103b ..........................30 sccr1 ................ sci control 1 ................................................................$102c ..........................46 sccr2 ................ sci control 2 ................................................................$102d ..........................46 scdr .................. serial communications data register...........................$102f ..........................48 scsr .................. sci status......................................................................$102e ..........................47 spcr .................. serial peripheral control ...............................................$1028 ..........................50 spdr .................. spi data .......................................................................$102a ..........................51 spsr .................. serial peripheral status .................................................$1029 ..........................51 tcnt................... timer count ..................................................................$100e, $100f ..............59 tctl1 ................. timer control 1 ..............................................................$1020 ..........................60 tctl2 ................. timer control 2 ..............................................................$1021 ..........................61 test1 ................. factory test ..................................................................$103e ..........................24 tflg1 ................. timer interrupt flag 1 ...................................................$1023 ..........................61 tflg2 ................. timer interrupt flag 2 ...................................................$1025 ................... 62 , 65 ti4o5 .................. timer input capture 4/output compare 5 ....................$101e, $101f ..............60 tic1?ic3........... timer input capture ......................................................$1010?1015 ..............60 tmsk1 ................ timer interrupt mask 1 ..................................................$1022 ..........................61 tmsk2 ................ timer interrupt mask 2 ..................................................$1024 ................... 62 , 64 toc1?oc4 ....... timer output compare .................................................$1016?101d ..............60 register index
motorola mc68hc11f1/fc0 6 MC68HC11FTS/d 1.3 block diagrams figure 1 mc68hc11f1 block diagram power clock logic interrupt logic mode control oscillator pulse pai/0c1 ddra port a cop timer system oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5/oc1 ic3 ic2 ic1 periodic interrupt irq xirq reset moda/ lir modb/ v stby ddrg port g pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 cspr og csgen csio1 csio2 chip selects 1024 bytes static ram cpu core ddrd port d accumulator sci spi pd0 pd1 pd2 pd3 pd4 pd5 rxd txd miso mosi sck ss pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port b addr15 addr14 addr13 addr12 addr10 addr9 addr8 port f pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr11 data0 data1 data2 data3 data4 data5 data6 address bus data bus e 4xout xtal extal v dd v ss data7 port e a/d converter pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 an7 an6 an5 an4 an3 an2 an1 an0 v rh v rl 512 bytes eeprom port c ddrc r/w
mc68hc11f1/fc0 motorola MC68HC11FTS/d 7 figure 2 mc68hc11fc0 block diagram power clock logic interrupt logic mode control oscillator pulse pai/0c1 ddra port a cop timer system oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5/oc1 ic3 ic2 ic1 periodic interrupt irq xirq reset moda / lir modb / v stby ddrg port g pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 cspr og csgen csio1 csio2 chip selects 1024 bytes static ram cpu core ddrd port d port e pe6 pe5 pe4 pe3 pe2 pe1 accumulator sci spi pd0 pd1 pd2 pd3 pd4 pd5 rxd txd miso mosi sck ss pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 port b addr15 addr14 addr13 addr12 addr10 addr9 addr8 port f pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr11 data0 data1 data2 data3 data4 data5 data6 address bus data bus e 4xout xtal extal v dd v ss ds data7 port c ddrc r/w wait
motorola mc68hc11f1/fc0 8 MC68HC11FTS/d 2 pin assignments and signal descriptions 2.1 mc68hc11f1 pin assignments figure 3 mc68hc11f1 68-pin plcc pin assignments pe4/an4 pe0/an0 pf0/addr0 pf1/addr1 pf2/addr2 pf4/addr4 pf5/addr5 pf6/addr6 pf7/addr7 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pc0/data0 4xout xtal extal r/w e moda /lir modb/ v stby v ss v rh v rl pe7/an7 pe3/an3 pe6/an6 pe2/an2 pe5/an5 pc1/data1 pc2/data2 pc3/data3 pc4/data4 pc5/data5 pc6/data6 pc7/data7 reset xirq irq pg7/csprog pg6/csgen pg5/csio1 pg4/csio2 pg3 pg2 pg0 29 pd0/rxd 30 pd1/txd 31 pd2/miso 32 pd3/mosi 33 pd4/sck 34 pd5/ss 35 v dd 36 pa7/pai/oc1 37 pa6/oc2/oc1 38 pa5/oc3/oc1 39 pa4/oc4/oc1 40 pa3/oc5/ic4/oc1 41 pa2/ic1 42 pa1/ic2 27 pa0/ic3 28 pf3/addr3 mc68hc11f1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 pg1 26 43 pb7/addr15 pb6/addr14 44 pe1/an1 61 45
mc68hc11f1/fc0 motorola MC68HC11FTS/d 9 figure 4 pin assignments for the mc68hc11f1 80-pin qfp nc pg1 pg2 pg3 pg4/csio2 pg5/csio1 pg6/csgen irq xirq reset pc7/data7 pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 pc1/data1 nc nc nc nc pb7/addr15 pa0/ic3 pa1/ic2 pa2/ic1 pa3/oc5/ic4/oc1 pa4/oc4/oc1 pa5/oc3/oc1 pa6/oc2/oc1 pa7/pai/oc1 v dd pd5/ss pd4/sck pd3/mosi pd2/miso pd1/txd pd0/rxd pg0 nc nc nc 21 nc 22 pe1/an1 23 pe5/an5 24 pe2an2 25 pe6/an6 26 pe3/an3 27 pe7/an7 28 v rl 29 v rh 30 v ss 31 modb/v stby 32 moda/lir 33 e34 r/w 35 extal 36 xtal 37 nc 38 4xout 39 pc0/data0 40 pg7/cspr og mc68hc11f1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pb6/addr14 pb5/addr13 pb4/addr12 nc pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pf7/addr7 pf6/addr6 pf5/addr5 pf4/addr4 pf3/addr3 pf2/addr2 pf1/addr1 pf0/addr0 pe0/an0 pe4/an4 nc
motorola mc68hc11f1/fc0 10 MC68HC11FTS/d 2.2 mc68hc11fc0 pin assignments figure 5 mc68hc11fc0 64-pin qfp pin assignments pc0/data0 xtal extal r/w e modb/v stby v ss moda/lir wait v dd pe3 pe6 pe2 pe5 pe1 pg2 pg3 pg4/csio2 pg5/csio1 pg6/csgen pg7/cspr og irq xirq reset pc7/data7 pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 pc1/data1 pd0/rxd pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/ic4/oc5/oc1 pa2/ic1 pa1/ic2 pa0/ic3 pb7/addr15 pb6/addr14 3 pb5/addr13 4 pb4/addr12 5 pb3/addr11 6 pb2/addr10 7 pb1/addr9 8 pb0/addr8 9 pf7/addr7 10 pf6/addr6 11 pf5/addr5 12 pf4/addr4 13 pf3/addr3 14 pf2/addr2 15 pf1/addr1 16 pf0/addr0 1 v ss 2 ds mc68hc11fc0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
mc68hc11f1/fc0 motorola MC68HC11FTS/d 11 figure 6 mc68hc11fc0 80-pin tqfp pin assignments pc0/data0 4xout nc xtal extal r/w e modb/v stby v ss moda/lir wait v dd pe3 pe6 pe2 pe5 pe1 nc nc nc pg1 pg2 pg3 pg4/csio0 pg5/csio1 pg6/csgen pg7/cspr og irq xirq reset pc7/data7 pc6/data6 pc5/data5 pc4/data4 pc3/data3 pc2/data2 pc1/data1 nc nc nc pd0/r x d pd1/t x d pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/ic4/oc5/oc1 pa2/ic1 pa1/ic2 pa0/ic3 pb7/addr15 nc nc 1 nc 2 pb6/addr14 3 pb5/addr13 4 pb4/addr12 5 pb3/addr11 6 pb2/addr10 7 pb1/addr9 8 pb0/addr8 9 pf7/addr7 10 pf6/addr6 11 pf5/addr5 12 pf4/addr4 13 pf3/addr3 14 pf2/addr2 15 pf1/addr1 16 pf0/addr0 17 v ss 18 pe4 19 nc 20 pg0 ds mc68hc11fc0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
motorola mc68hc11f1/fc0 12 MC68HC11FTS/d 2.3 pin descriptions v dd and v ss v dd is the positive power input to the mcu, and v ss is ground. reset this active-low input initializes the mcu to a known startup state. it also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or the cop watchdog circuits. xtal and extal these two pins provide the interface for either a crystal or a cmos-compatible clock to drive the internal clock circuitry. the frequency applied to these pins is four times the desired bus frequency (e clock). e this pin provides an output for the e clock, the basic timing reference signal for the bus circuitry. the address bus is active when e is low, and the data bus is active when e is high. ds the data strobe output is the inverted e clock. ds is present on the mc68hc11fc0 only. wait this input is used to stretch the bus cycle to accomodate slower devices. the mcu samples the logic level at this pin on the rising edge of e clock. if it is high, the mcu holds the e clock high for the next four extal clock cycles. if it is low, the e clock responds normally, going low two extal cycles later. the wait pin is present on the mc68hc11fc0 only . 4xout this pin provides a buffered oscillator signal to drive another m68hc11 mcu. the 4xout pin is not present on the 64-pin qfp mc68hc11fc0 package . irq this active-low input provides a means of generating asynchronous, maskable interrupt requests for the cpu. xirq this interrupt request input can be made non-maskable by clearing the x bit in the mcu? condition code register. moda/lir and modb/vstby the logic level applied to the moda and modb pins at reset determines the mcu? opreating mode (see table 7 in 4 operating modes and system initialization ). after reset, moda functions as lir , an open-drain output that indicates the start of an instruction cycle. modb functions as v stby , providing a backup battery to maintain the contents of ram when v dd falls. r/w in expanded and test modes, r/w indicates the direction of transfers on the external data bus. v rh and v rl these pins provide the reference voltage for the analog-to-digital converter. use bypass capacitors to minimize noise on these signals. any noise on v rh and v rl will directly affect a/d accuracy. these pins are not present on the mc68hc11fc0.
mc68hc11f1/fc0 motorola MC68HC11FTS/d 13 port signals on the mc68hc11f1, 54 pins are arranged into six 8-bit ports (ports a, b, c, e, f, and g) and one 6-bit port (port d). on the mc68hc11fc0, either 52 or 49 pins are available, depending on the package. general-purpose i/o port signals are discussed briefly in the following pragraphs. for additional information, refer to 7 parallel input/output . port a pins port a is an 8-bit general-purpose i/o port (pa[7:0]) with a data register (porta) and a data direction register (ddra). port a pins share functions with the 16-bit timer system. out of reset, pa[7:0] are general-purpose high-impedance inputs. port b pins port b is an 8-bit output-only port. in single-chip modes, port b pins are general-purpose output pins (pb[7:0]). in expanded modes, port b pins act as the high-order address lines addr[15:8]. port c pins port c is an 8-bit general-purpose i/o port with a data register (portc) and a data direction register (ddrc). in single-chip modes, port c pins are general-purpose i/o pins pc[7:0]. in expanded modes, port c pins are configured as data bus pins data[7:0]. port d pins port d is a 6-bit general-purpose i/o port with a data register (portd) and a data direction register (ddrd). the six port d lines pd[5:0] can be used for general-purpose i/o or for the serial communications interface (sci) or serial peripheral interface (spi) subsystems. port e pins port e is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital converter. port e pins that are not used for the a/d system can be used as general-purpose inputs. however, porte should not be read during the sample portion of an a/d conversion sequence. note the a/d system is not available on the mc68hc11fc0. pe7 and pe0 are not available on the 80-pin mc68hc11fc0. pe7, pe4, and pe0 are not available on the 64-pin mc68hc11fc0. port f pins port f is an 8-bit output-only port. in single-chip mode, port f pins are general-purpose output pins pf[7:0]. in expanded mode, port f pins act as the low-order address outputs addr[7:0]. port g pins port g is an 8-bit general-purpose i/o port. when enabled, four chip select signals are alternate functions of pg[7:4]. note pg[1:0] are not available on the 64-pin mc68hc11fc0.
motorola mc68hc11f1/fc0 14 MC68HC11FTS/d 3 control registers the mc68hc11f1 and mc68hc11fc0 control registers determine most of the system? operating characteristics. they occupy a 96-byte relocatable memory block. their names and bit mnemonics are summarized in the following table. addresses shown are the default locations out of reset. 3.1 mc68hc11f1 control registers table 5 mc68hc11f1 register and control bit assignments bit 7 654321 bit 0 $1000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $1001 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra $1002 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg $1003 ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg $1004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $1005 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf $1006 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $1007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $1008 0 0 pd5 pd4 pd3 pd2 pd1 pd0 portd $1009 0 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd $100a pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $100b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $100c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $100d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $100e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $100f bit 7 654321 bit 0 tcnt (low) $1010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $1011 bit 7 654321 bit 0 tic1 (low) $1012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $1013 bit 7 654321 bit 0 tic2 (low) $1014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $1015 bit 7 654321 bit 0 tic3 (low) $1016 bit 15 14 13 12 11 10 9 bit 8 toc1 (high) $1017 bit 7 654321 bit 0 toc1 (low) $1018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $1019 bit 7 654321 bit 0 toc2 (low) $101a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $101b bit 7 654321 bit 0 toc3 (low) $101c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $101d bit 7 654321 bit 0 toc4 (low) $101e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (high) $101f bit 7 654321 bit 0 ti4/o5 (low) $1020 om2 ol2 om3 ol3 om4 ol4 om5 ol5 tctl1 $1021 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a tctl2
mc68hc11f1/fc0 motorola MC68HC11FTS/d 15 $1022 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tmsk1 $1023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $1024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $1025 tof rtif paovf paif 0000 tflg2 $1026 0 paen pamod pedge 0 i4/05 rtr1 rtr0 pactl $1027 bit 7 654321 bit 0 pacnt $1028 spie spe dwom mstr cpol cpha spr1 spr0 spcr $1029 spif wcol 0 modf 0000 spsr $102a bit 7 654321 bit 0 spdr $102b tclr scp2 scp1 scp0 rckb scr2 scr1 scr0 baud $102c r8 t8 0 m wake 0 0 0 sccr1 $102d tie tcie rie ilie te re rwu sbk sccr2 $102e tdre tc rdrf idle or nf fe 0 scsr $102f bit 7 654321 bit 0 scdr $1030 ccf 0 scan mult cd cc cb ca adctl $1031 bit 7 654321 bit 0 adr1 $1032 bit 7 654321 bit 0 adr2 $1033 bit 7 654321 bit 0 adr3 $1034 bit 7 654321 bit 0 adr4 $1035 0 0 0 ptcon bprt3 bprt2 bprt1 bprt0 bprot $1036 reserved $1037 reserved $1038 gwom cwom clk4x lirdv 0 sprbyp 0 0 opt2 $1039 0 0 irqe dly cme fcme cr1 cr0 option $103a bit 7 654321 bit 0 coprst $103b odd even 0 byte row erase eelat eepgm pprog $103c rboot smod mda irv psel3 psel2 psel1 psel0 hprio $103d ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 init $103e tilop 0 occr cbyp disr fcm fcop 0 test1 $103f ee3 ee2 ee1 ee0 1 nocop 1 eeon config $1040 reserved to $105b reserved $105c i01sa i01sb i02sa i02sb gstha gstgb pstha psthb csstrh $105d i01en i01pl i02en i02pl gcspr pcsen psiza psizb csctl $105e ga15 ga14 ga13 ga12 ga11 ga10 0 0 csgadr $105f i01av i02av 0 gnpol gavld gsiza gsizb gsizc csgsiz table 5 mc68hc11f1 register and control bit assignments (continued) bit 7 654321 bit 0
motorola mc68hc11f1/fc0 16 MC68HC11FTS/d 3.2 mc68hc11fc0 control registers table 6 mc68hc11fc0 register and control bit assignments bit 7 654321 bit 0 $1000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $1001 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra $1002 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 portg $1003 ddg7 ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 ddrg $1004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $1005 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 portf $1006 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $1007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $1008 0 0 pd5 pd4 pd3 pd2 pd1 pd0 portd $1009 0 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd $100a pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $100b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $100c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $100d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $100e bit 15 14 13 12 11 10 9 bit 8 tcnt (high) $100f bit 7 654321 bit 0 tcnt (low) $1010 bit 15 14 13 12 11 10 9 bit 8 tic1 (high) $1011 bit 7 654321 bit 0 tic1 (low) $1012 bit 15 14 13 12 11 10 9 bit 8 tic2 (high) $1013 bit 7 654321 bit 0 tic2 (low) $1014 bit 15 14 13 12 11 10 9 bit 8 tic3 (high) $1015 bit 7 654321 bit 0 tic3 (low) $1016 bit 15 14 13 12 11 10 9 bit 8 toc1 (high) $1017 bit 7 654321 bit 0 toc1 (low) $1018 bit 15 14 13 12 11 10 9 bit 8 toc2 (high) $1019 bit 7 654321 bit 0 toc2 (low) $101a bit 15 14 13 12 11 10 9 bit 8 toc3 (high) $101b bit 7 654321 bit 0 toc3 (low) $101c bit 15 14 13 12 11 10 9 bit 8 toc4 (high) $101d bit 7 654321 bit 0 toc4 (low) $101e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (high) $101f bit 7 654321 bit 0 ti4/o5 (low) $1020 om2 ol2 om3 ol3 om4 ol4 om5 ol5 tctl1 $1021 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a tctl2 $1022 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tmsk1 $1023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $1024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $1025 tof rtif paovf paif 0000 tflg2
mc68hc11f1/fc0 motorola MC68HC11FTS/d 17 $1026 0 paen pamod pedge 0 i4/05 rtr1 rtr0 pactl $1027 bit 7 654321 bit 0 pacnt $1028 spie spe dwom mstr cpol cpha spr1 spr0 spcr $1029 spif wcol 0 modf 0000 spsr $102a bit 7 654321 bit 0 spdr $102b tclr scp2 scp1 scp0 rckb scr2 scr1 scr0 baud $102c r8 t8 0 m wake 0 0 0 sccr1 $102d tie tcie rie ilie te re rwu sbk sccr2 $102e tdre tc rdrf idle or nf fe 0 scsr $102f bit 7 654321 bit 0 scdr $1030 reserved to $1037 reserved $1038 gwom cwom clk4x lirdv 0 sprbyp 0 0 opt2 $1039 0 0 irqe dly cme fcme cr1 cr0 option $103a bit 7 654321 bit 0 coprst $103b reserved $103c rboot smod mda irv psel3 psel2 psel1 psel0 hprio $103d ram5 ram4 ram3 ram2 ram1 ram0 reg1 reg0 init $103e tilop 0 occr cbyp disr fcm fcop 0 test1 $103f 00000 nocop 0 0 config $1040 reserved to $105b reserved $105c i01sa i01sb i02sa i02sb gstha gstgb pstha psthb csstrh $105d i01en i01pl i02en i02pl gcspr pcsen psiza psizb csctl $105e ga15 ga14 ga13 ga12 ga11 ga10 0 0 csgadr $105f i01av i02av 0 gnpol gavld gsiza gsizb gsizc csgsiz table 6 mc68hc11fc0 register and control bit assignments (continued) bit 7 654321 bit 0
motorola mc68hc11f1/fc0 18 MC68HC11FTS/d 4 operating modes and system initialization the 16-bit address bus can access 64 kbytes of memory. because the mc68hc11f1 and mc68hc11fc0 are intended to operate principally in expanded mode, there is no internal rom and the address bus is non-multiplexed. both devices include 1 kbyte of static ram, a 96-byte control reg- ister block, and 256 bytes of bootstrap rom. the mc68hc11f1 also includes 512 bytes of eeprom. ram and registers can be remapped on both the mc68hc11f1 and the mc68hc11fc0. on both the mc68hc11f1 and the mc68hc11fc0, out of reset ram resides at $0000 to $03ff and registers re- side at $1000 to $105f. on the mc68hc11f1, ram and registers can both be remapped to any 4- kbyte boundary. on the mc68hc11fc0, ram can be remapped to any 1-kbyte boundary, and regis- ters can be remapped to any 4-kbyte boundary in the first 16 kbytes of address space. ram and control register locations are defined by the init register, which can be written only once with- in the first 64 e-clock cycles after a reset in normal modes. it becomes a read-only register thereafter. if ram and the control register block are mapped to the same boundary, the register block has priority of the first 96 bytes. in expanded and special test modes in the mc68hc11f1, eeprom is located from $ x e00 to $ x fff, where x represents the value of the four high-order bits of the config register. eeprom is enabled by the eeon bit of the config register. in single-chip and bootstrap modes, the eeprom is located from $fe00 to $ffff. 4.1 operating modes bootstrap rom resides at addresses $bf00?bfff, and is only available when the mcu operates in special bootstrap operating mode. operating modes are determined by the logic levels applied to the modb and moda pins at reset. in single-chip mode, the mcu functions as a self-contained microcontroller and has no external address or data bus. ports b, c and f are available for general-purpose i/o (gpio). ports b and f are outputs only; each of the port c pins can be configured as input or output. caution the mc68hc11fc0 must not be configured to boot in single-chip mode because it has no internal rom or eeprom. operation of the device in single-chip mode will result in erratic behavior. in expanded mode, the mcu can access external memory. ports b and f provide the address bus, and port c is the data bus. special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap rom. in this mode, the user can download a program into on-chip ram through the serial communica- tion interface (sci). special test mode, a variation of expanded mode, is primarily used during motorola? internal production testing, but can support emulation and debugging during program development. table 7 shows a summary of operating modes, mode select pins, and control bits in the hprio register. table 7 hardware mode select summary input pins mode description control bits in hprio (latched at reset) modb moda rboot smod mda 1 0 single chip 0 0 0 1 1 expanded 0 0 1 0 0 special bootstrap 1 1 0 0 1 special test 0 1 1
mc68hc11f1/fc0 motorola MC68HC11FTS/d 19 4.2 memory maps notes: 1. ram can be remapped to any 4-kbyte boundary ($x000). ??represents the value contained in ram[3:0] in the init register. 2. the register block can be remapped to any 4-kbyte boundary ($y000). ??represents the value contained in reg[3:0] in the init register. 3. special test mode vectors are externally addressed. 4. in special test mode the address locations $zd00?zdff are not externally addressable. ??represents the val- ue of bits ee[3:0] in the config register. 5. eeprom can be remapped to any 4-kbyte boundary ($z000). ??represents the value contained in ee[3:0] in the config register. figure 7 mc68hc11f1 memory map $0000 $03ff $1000 $105f $ffc0 $ffff single chip moda = 0 modb = 1 expanded moda = 1 modb = 1 special test moda = 1 modb = 0 special bootstrap moda = 0 modb = 0 $bf00 $bfff external external external external special mode vectors 3 $bfc0 $bfff normal mode vectors $ffff $fe00 ? 512 bytes eeprom 5 reserved 4 interrupt interrupt 1024 bytes ram 1 x000 x3ff 96-byte register file 2 y000 y05f $ffc0 256 bytes bootstrap rom
motorola mc68hc11f1/fc0 20 MC68HC11FTS/d notes: 1. ram can be remapped to any 1-kbyte boundary, depending on the value contained in the ram field in the init register. 2. the register block can be remapped to $0000, $2000, or $3000, depending on the value contained in reg[1:0] in the init register. figure 8 mc68hc11fc0 memory map 4.3 system initialization registers hprio ? highest priority interrupt and miscellaneous $x03c bit 7 654321 bit 0 rboot smod mda irv psel3 psel2 psel1 psel0 reset: 0 0 0 0 0 1 0 1 single-chip 0 0 1 0 0 1 0 1 expanded 1 1 0 1 0 1 0 1 bootstrap 0 1 1 1 0 1 0 1 special test $0000 $03ff $1000 $105f $ffc0 $ffff single chip moda = 0 modb = 1 expanded moda = 1 modb = 1 special test moda = 1 modb = 0 special bootstrap moda = 0 modb = 0 $bf00 $bfff external external external external special mode vectors $bfc0 $bfff normal mode vectors $ffff $fe00 ? interrupt interrupt 1024 bytes ram 1 96-byte register file 2 $ffc0 256 bytes bootstrap rom
mc68hc11f1/fc0 motorola MC68HC11FTS/d 21 rboot ?read bootstrap rom rboot is valid only when smod is set to one (special bootstrap or special test mode). rboot can only be written in special modes but can be read anytime. 0 = boot loader rom disabled and not in memory map 1 = boot loader rom enabled and in memory map at $bf00?bfff smod and mda ? special mode select and mode select a the initial value of smod is the inverse of the logic level present on the modb pin at the rising edge of reset. the initial value of mda equals the logic level present on the moda pin at the rising edge of reset. these two bits can be read at any time. they can be written at any time in special modes. neither bit can be written in normal modes. smod cannot be set once it has been cleared. refer to table 8 . irv ?internal read visibility this bit can be read at any time. it can be written at any time in special modes, but only once in normal modes. in single-chip and bootstrap modes, irv has no meaning or effect. 0 = internal reads not visible 1 = data from internal reads is driven on the external data bus psel[3:0] ?see 5.2 reset and interrupt registers , page 27. the init register can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. note the register diagram above applies to the mc68hc11fc0 only. a diagram and bit descriptions of the init register in the mc68hc11f1 are provided elsewhere in this section. ram[5:0] ?internal ram map position these bits determine the upper six bits of the ram address and allow mapping of the ram to any one- kbyte boundary. reg[1:0] ?register block map position these bits determine the location of the register block, as shown in table 9 . table 8 hardware mode select summary input pins mode description control bits in hprio (latched at reset) modb moda rboot smod mda 1 0 single chip 0 0 0 1 1 expanded 0 0 1 0 0 special bootstrap 1 1 0 0 1 special test 0 1 1 init ? ram and i/o mapping ( mc68hc11fc0 only ) $x03d bit 7 6 5 4 3 2 1 bit 0 ram5 ram4 ram3 ram2 ram1 ram0 reg1 reg0 reset: 0 0 0 0 0 0 0 1 table 9 register block location reg[1:0] register block address 0 0 $0000 ?$005f 0 1 $1000 ?$105f 1 0 $2000 ?$205f 1 1 $3000 ?$305f
motorola mc68hc11f1/fc0 22 MC68HC11FTS/d the init register can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. note the register diagram above applies to the mc68hc11f1 only. a diagram and bit descriptions of the init register in the mc68hc11fc0 are provided elsewhere in this section. ram[3:0] ?internal ram map position these bits determine the upper four bits of the ram address and allow mapping of the ram to any four- kbyte boundary. refer to table 10 . reg[3:0] ?96-byte register block map position these bits determine bits the upper 4 bits of the register block and allow mapping of the register block to any four-kbyte boundary. refer to table 10 . gwom port g wired-or mode option refer to 7.8 parallel i/o registers , page 36. init ? ram and i/o mapping ( mc68hc11f1 only ) $x03d bit 7 6 5 4 3 2 1 bit 0 ram3 ram2 ram1 ram0 reg3 reg4 reg1 reg0 reset: 0 0 0 0 0 0 0 1 table 10 ram and register mapping ram[3:0] location reg[3:0] location 0000 $0000-$03ff 0000 $0000-$005f 0001 $1000-$13ff 0001 $1000-$105f 0010 $2000-$23ff 0010 $2000-$205f 0011 $3000-$33ff 0011 $3000-$305f 0100 $4000-$43ff 0100 $4000-$405f 0101 $5000-$53ff 0101 $5000-$505f 0110 $6000-$63ff 0110 $6000-$605f 0111 $7000-$73ff 0111 $7000-$705f 1000 $8000-$83ff 1000 $8000-$805f 1001 $9000-$93ff 1001 $9000-$905f 1010 $a000-$a3ff 1010 $a000-$a05f 1011 $b000-$b3ff 1011 $b000-$b05f 1100 $c000-$c3ff 1100 $c000-$c05f 1101 $d000-$d3ff 1101 $d000-$d05f 1110 $e000-$e3ff 1110 $e000-$e05f 1111 $f000-$f3ff 1111 $f000-$f05f opt2 ? system configuration option register 2 $x038 bit 7 6 5 4 3 2 1 bit 0 gwom cwom clk4x lirdv sprbyp reset 0 0 1 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 23 cwom ?port c wired-or mode option refer to 7.8 parallel i/o registers , page 37. clk4x ?4xclk output enable this bit can only be written once after reset in all modes. 0 = 4xout clock output is disabled 1 = buffered oscillator is driven on the 4xout clock output lirdv ?load instruction register driven in order to detect consecutive instructions in a high-speed application, lir can be driven high for one quarter of an e-clock cycle during each instruction fetch. 0 = lir signal is not driven high. 1 = lir signal is driven high. bits 3, 1, 0 ?not implemented. reads always return zero and writes have no effect. sprbyp see 10.2 spi registers , page 52. *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. adpu ?a/d power-up this bit is implemented on the mc68hc11f1 only . on the mc68hc11fc0, reads always return zero and writes have no effect. 0 = a/d system disabled 1 = a/d system enabled csel ?clock select this bit is implemented on the mc68hc11f1 only . on the mc68hc11fc0, reads always return zero and writes have no effect. 0 = a/d and eeprom use system e clock 1 = a/d and eeprom use internal rc clock irqe ?irq select edge sensitive only 0 = low level recognition 1 = falling edge recognition dly ?enable oscillator start-up delay on exit from stop 0 = no stabilization delay on exit from stop 1 = stabilization delay of 4064 e-clock cycles is enabled on exit from stop cme ?clock monitor enable 0 = clock monitor disabled; slow clocks can be used 1 = slow or stopped clocks cause clock failure reset fcme ?force clock monitor enable 0 = clock monitor circuit follows the state of the cme bit 1 = clock monitor circuit is enabled until the next reset in order to use both stop and the clock monitor, the cme bit should be written to zero prior to executing a stop instruction and rewritten to one after recovery from stop. fcme should be kept cleared if the user intends to use the stop instruction. cr[1:0] ?cop timer rate select refer to 5.2 reset and interrupt registers , page 27. option ? system configuration options $x039 bit 7 6 5 4 3 2 1 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0 0 0 1 0 0 0 0
motorola mc68hc11f1/fc0 24 MC68HC11FTS/d u = unaffected by reset bits 7:3 ?see 6.2 eeprom registers , page 30. (these bits are implemented on the mc68hc11f1 only.) nocop ?cop system disable 0 = cop enabled (forces reset on time-out) 1 = cop disabled (does not force reset on time-out) these bits can only be written in test and bootstrap modes. tilop ?test illegal opcode this test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal opcode is fetched. 0 = normal operation (trap on illegal opcodes) 1 = inhibit lir when an illegal opcode is found bit 6 ?not implemented. reads always return zero and writes have no effect. occr ?output condition code register to timer port 0 = normal operation 1 = condition code bits h, n, z, v and c are driven on pa[7:3] to allow a test system to monitor cpu operation cbyp ?timer divider chain bypass 0 = normal operation 1 = the 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. the system e clock drives both halves directly. disr ?disable resets from cop and clock monitor in test and bootstrap modes, this bit is reset to one to inhibit clock monitor and cop resets. in normal modes, disr is reset to zero. 0 = normal operation 1 = cop and clock monitor failure do not generate a system reset fcm ?force clock monitor failure 0 = normal operation 1 = generate an immediate clock monitor failure reset. note that the cme bit in the option register must also be set in order to force the reset. fcop ?force cop watchdog failure 0 = normal operation 1 = generate an immediate cop failure reset. note that the nocop bit in the config register must be cleared (cop enabled) in order to force the reset. bit 0 ?not implemented. reads always return zero and writes have no effect. config ? eeprom mapping, cop, eeprom enables $x03f bit 7 654321 bit 0 ee3 ee2 ee1 ee0 1 nocop 1 eeon reset uuuu1u1 u test1 ? factory test $x03e bit 7 6 5 4 3 2 1 bit 0 tilop 0 occr cbyp disr fcm fcop 0 reset: 0 0 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 25 5 resets and interrupts there are three sources of reset on the mc68hc11f1 and mc68hc11fc0, each having its own reset vector: ?reset pin ?clock monitor failure ?computer operating properly (cop) failure there are 22 interrupt sources serviced by 18 interrupt vectors. (the sci interrupt vector services five sci interrupt sources.) three of the interrupt vectors are non-maskable: ?illegal opcode trap ?software interrupt ?xirq pin (pseudo non-maskable interrupt) the other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. maskable in- terrupts are recognized only if the global interrupt mask bit (i) in the condition code register (ccr) is clear. maskable interrupts have a default priority arrangement out of reset. however, any one interrupt source can be elevated to the highest maskable priority position by writing to the hprio register. this register can be written at any time, provided the i bit in the ccr is set. in addition to the global i bit, all maskable interrupt sources except the external interrupt (irq pin) are subject to local enable bits in control registers. each of these interrupt sources also sets a correspond- ing flag bit in a control register that can be polled by software. several of these flags are automatically cleared during the normal course of responding to the interrupt requests. for example, the rdrf flag is set when a byte has been received in the sci. the normal response to an rdrf interrupt request is to read the sci status register to check for receive errors, then to read the received data from the sci data register. it is precisely these two steps that are required to clear the rdrf flag, so no further instructions are necessary. 5.1 interrupt sources the following table summarizes the interrupt sources, vector addresses, masks, and flag bits.
motorola mc68hc11f1/fc0 26 MC68HC11FTS/d 5.2 reset and interrupt registers *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. bits [7:6], [4:2] refer to 4.3 system initialization registers , page 23, and 11.3 a/d registers , page 56. irqe ?irq select edge sensitive only 0 = low level recognition 1 = falling edge recognition table 11 interrupt and reset vector assignments vector address interrupt source ccr mask local mask flag bit ffc0, c1 to ffd4, d5 reserved ffd6, d7 sci serial system i bit sci transmit complete tcie tc sci transmit data register empty tie tdre sci idle line detect ilie idle sci receiver overrun rie or sci receive data register full rie rdrf ffd8, d9 spi serial transfer complete i bit spie spif ffda, db pulse accumulator input edge i bit paii paif ffdc, dd pulse accumulator overflow i bit paovi paovf ffde, df timer overflow i bit toi tof ffe0, e1 timer input capture 4/output compare 5 i bit i4/o5i i4/o5f ffe2, e3 timer output compare 4 i bit oc4i oc4f ffe4, e5 timer output compare 3 i bit oc3i oc3f ffe6, e7 timer output compare 2 i bit oc2i oc2f ffe8, e9 timer output compare 1 i bit oc1i oc1f ffea, eb timer input capture 3 i bit ic3i ic3f ffec, ed timer input capture 2 i bit ic2i ic2f ffee, ef timer input capture 1 i bit ic1i ic1f fff0, f1 real-time interrupt i bit rtii rtif fff2, f3 irq i bit none none fff4, f5 xirq pin x bit none none fff6, f7 software interrupt none none none fff8, f9 illegal opcode trap none none none fffa, fb cop failure none nocop none fffc, fd clock monitor fail none cme none fffe, ff reset none none none option ? system configuration options $x039 bit 7 6 5 4 3 2 1 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0 0 0 1 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 27 cr[1:0] ?cop timer rate select the cop system is driven by a constant frequency of e/2 15 . cr[1:0] specify an additional divide-by fac- tor to arrive at the cop time-out rate. write $55 to coprst to arm the cop watchdog clearing mechanism. then write $aa to coprst to reset the cop timer. performing instructions between these two steps is possible provided both steps are completed in the correct sequence before the timer times out. bits [7:4] ?see 4.3 system initialization registers , page 20. psel[3:0] ?interrupt priority select bits can be written only while the i bit in the ccr is set (interrupts disabled). these bits select one interrupt source to have priority over other i-bit related sources. table 12 cop watchdog time-out periods frequency tolerance cr[1:0] = 00 cr[1:0] = 01 cr[1:0] = 10 cr[1:0] = 11 1 mhz -0/+32.768 ms 32.768 ms 131.072 ms 524.288 ms 2.097 s 2 mhz -0/+16.384 ms 16.384 ms 65.536 ms 262.144 ms 1.049 s 3 mhz -0/+10.923 ms 10.923 ms 43.691 ms 174.763 ms 699.051 ms 4 mhz -0/+8.192 ms 8.192 ms 32.768 ms 131.072 ms 524.288 ms 5 mhz -0/+6.554 ms 6.554 ms 26.214 ms 104.858 ms 419.430 ms 6 mhz -0/+5.461 ms 5.461 ms 21.845 87.381 ms 349.525 ms any e -0/+2 15 /e 2 15 /e 2 17 /e 2 19 /e 2 21 /e coprst ? arm/reset cop timer circuitry $x03a bit 7 6 5 4 3 2 1 bit 0 7 6 5 4 3 2 1 0 reset: 0 0 0 0 0 0 0 0 hprio ? highest priority i-bit interrupt and miscellaneous $x03c bit 7 654321 bit 0 rboot smod mda irv psel3 psel2 psel1 psel0 reset: 0101 table 13 highest priority interrupt selection psel[3:0] interrupt source promoted 0000 timer overflow 0001 pulse accumulator overflow 0010 pulse accumulator input edge 0011 spi serial transfer complete 0100 sci serial system 0101 reserved (default to irq ) 0110 irq (external pin) 0111 real-time interrupt 1000 timer input capture 1 1001 timer input capture 2 1010 timer input capture 3
motorola mc68hc11f1/fc0 28 MC68HC11FTS/d bits 7:3, 1:0 ?see 6.2 eeprom registers , page 30. nocop ?cop system disable 0 = cop enabled (forces reset on time-out) 1 = cop disabled (does not force reset on time-out) 1011 timer output compare 1 1100 timer output compare 2 1101 timer output compare 3 1110 timer output compare 4 1111 timer output compare 5/input capture 4 config ? eeprom mapping, cop, eeprom enables $x03f bit 7 6 5 4 3 2 1 bit 0 ee3 ee2 ee1 ee0 1 nocop 1 eeon reset u u u u 1 u 1 u table 13 highest priority interrupt selection (continued) psel[3:0] interrupt source promoted
mc68hc11f1/fc0 motorola MC68HC11FTS/d 29 6 electrically erasable programmable rom the mc68hc11f1 has 512 bytes of electrically erasable programmable rom (eeprom). a nonvola- tile, eeprom-based configuration register (config) controls whether the eeprom is present or ab- sent and determines its position in the memory map. in single-chip and bootstrap modes the eeprom is positioned at $fe00?ffff. in expanded and special test modes, the eeprom can be repositioned to any 4-kbyte boundary ($xe00?xfff). note eeprom is available on the mc68hc11f1 only. 6.1 eeprom operation the eeon bit in config controls whether the eeprom is present in the memory map. when eeon = 1, the eeprom is enabled. when eeon = 0, the eeprom is disabled and removed from the memory map. eeon is forced to one out of reset in single-chip and special bootstrap modes to enable eeprom. eeon is forced to zero out of reset in special test mode to remove eeprom from the mem- ory map, although test software can turn it back on. in normal expanded mode, eeon is reset to the value last programmed into config. an on-chip charge pump develops the high voltage required for programming and erasing. when the e-clock frequency is 1 mhz or above, the charge pump is driven by the e-clock. when the e-clock fre- quency is less than 1 mhz, select the internal rc oscillator to drive the eeprom charge pump by writ- ing one to the csel bit in the option register. refer to the discussion of the option register in 4.3 system initialization registers , page 23. 6.2 eeprom registers bits [7:5] ?not implemented. reads always return zero and writes have no effect. ptcon ?protect for config 0 = config register can be programmed or erased normally 1 = config register cannot be programmed or erased bprt[3:0] ?block protect bits for eeprom 0 = protection disabled 1 = protection enabled note block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special modes. block protect register bits can be written to one (protection enabled) at any time. bprot ? block protect $x035 bit 7 6 5 4 3 2 1 bit 0 0 0 0 ptcon bprt3 bprt2 bprt1 bprt0 reset 0 0 0 1 1 1 1 1 table 14 block protect bits for eeprom bit name block protected block size bprt3 $xee0?fff 288 bytes bprt2 $xe60?edf 128 bytes pbrt1 $xe20?e5f 64 bytes bprt0 $xe00?e1f 32 bytes
motorola mc68hc11f1/fc0 30 MC68HC11FTS/d odd ?program odd rows (test) even ?program even rows (test) row and byte ?row erase select bit and byte erase select the value of these bits determines the manner in which eeprom is erased. bit encodings are shown in 6.2 eeprom registers , page 30. erase ?erase/normal control for eeprom 0 = normal read or program mode 1 = erase mode eelat ?eeprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bus configured for programming or erasing eepgm ?eeprom program command 0 = program or erase voltage to eeprom array switched off 1 = program or erase voltage to eeprom array switched on u = unaffected by reset. the config register is used to assign eeprom a location in the memory map and to enable or disable eeprom operation. bits in this register are user-programmed except when forced to certain values, as noted in the following bit descriptions. ee[3:0] ?eeprom map position eeprom is located at $xe00 ?$xfff, where x is the value represented by these four bits. in single- chip and bootstrap modes, eeprom is forced to $fe00 ?$ffff, regardless of the state of these bits. on factory-fresh devices, ee[3:0] = $0. bit 3 ?not implemented. reads always return one and writes have no effect. nocop ?cop system disable 0 = cop enabled (forces reset on time-out) 1 = cop disabled (does not force reset on time-out) pprog ? eeprom programming control $x 03b bit 7 6 5 4 3 2 1 bit 0 odd even 0 byte row erase eelat eepgm reset 0 0 0 0 0 0 0 0 table 15 row and byte encodings byte row action 0 0 bulk erase (all 512 bytes) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase config ? eeprom mapping, cop, eeprom enables $x03f bit 7 6 5 4 3 2 1 bit 0 ee3 ee2 ee1 ee0 1 nocop 1 eeon reset u u u u 1 u 1 u
mc68hc11f1/fc0 motorola MC68HC11FTS/d 31 bit 1 ?not implemented. reads always return one and writes have no effect. eeon ?eeprom enable this bit is forced to one in single-chip and bootstrap modes. in test mode, eeon is forced to zero out of reset. in expanded mode, the eeprom obeys the state of this bit. 0 = eeprom is removed from the memory map. 1 = eeprom is present in the memory map. refer to 6.4 config register programming for instructions on programming this register. 6.3 eeprom programming and erasure programming and erasing the eeprom is controlled by the pprog register, subject to the block pro- tect (bprot) register value. to erase the eeprom, ensure that the proper bits of the bprot register are cleared, and then complete the following steps: 1. write to pprog with the erase and eelat bits set and the byte and row bits set or cleared as appropriate. 2. write to the appropriate eeprom address with any data. row erase ($xe00?xe0f, $xe10 $xe1f,... $xff0?xfff) requires a single write to any location in the row. perform bulk erase by writing to any location in the array. 3. write to pprog with the erase, eelat, and eepgm bits set and the byte and row bits set or cleared as appropriate. 4. delay for 10 ms (20 ms for low-voltage operation). 5. clear the eepgm bit in pprog to turn off the high voltage. 6. clear the pprog register to reconfigure eeprom address and data buses for normal opera- tions. to program the eeprom, ensure that the proper bits of the bprot register are cleared, and then com- plete the following steps: 1. write to pprog with the eelat bit set. 2. write data to the desired address. 3. write to pprog with the eelat and eepgm bits set. 4. delay for 10 ms (20 ms for low-voltage operation). 5. clear the eepgm bit in pprog to turn off the high voltage. 6. clear the pprog register to reconfigure eeprom address and data buses for normal opera- tions. 6.3.1 programming a byte the following example shows how to program an eeprom byte. this example assumes that the ap- propriate bits in bprot are cleared and that the data to be programmed is present in accumulator a. prog ldab #$02 eelat=1, eepgm=0 stab $103b set eelat bit staa $fe00 store data to eeprom address ldab #$03 eelat=1, eepgm=1 stab $103b turn on programming voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 6.3.2 bulk erase the following example shows how to bulk erase the 512-byte eeprom. the config register is not affected in this example. note that when the config register is bulk erased, config and the 512-byte array are all erased. bulke ldab #$06 erase=1, eelat=1, eepgm=0 stab $103b set eelat bit
motorola mc68hc11f1/fc0 32 MC68HC11FTS/d stab $fe00 store any data to any eeprom address ldab #$07 eelat=1, eepgm=1 stab $103b turn on programming voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 6.3.3 row erase the following example shows how to perform a fast erase of large sections of eeprom. this example assumes that index register x contains the address of a location in the desired row. rowe ldab #$0e row=1, erase=1, eelat=1, eepgm=0 stab $103b set to row erase mode stab $xxxx store any data to any address in row ldab #$0f row=1, erase=1, eelat=1, eepgm=1 stab $103b turn on high voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 6.3.4 byte erase the following is an example of how to erase a single byte of eeprom. this example assumes that in- dex register x contains the address of the byte to be erased. bytee ldab #$16 byte=1, row=0, erase=1, eelat=1, eepgm=0 stab $103b set to byte erase mode stab $0,x store any data to address to be erased ldab #$17 byte=1, row=0, erase=1, eelat=1, eepgm=1 stab $103b turn on high voltage jsr dly10 delay 10 ms clr $103b turn off high voltage and set to read mode 6.4 config register programming because the config register is implemented with eeprom cells, use eeprom procedures to erase and program this register. the procedure for programming is the same as for programming a byte in the eeprom array, except that the config register address is used. config can be programmed or erased (including byte erase) while the mcu is operating in any mode, provided that ptcon in bprot is clear. to change the value in the config register, complete the following procedure. do not initiate a reset until the procedure is complete. the new value will not take effect until after the next reset se- quence. 1. erase the config register. 2. program the new value to the config address. 3. initiate reset.
mc68hc11f1/fc0 motorola MC68HC11FTS/d 33 7 parallel input/output on the mc68hc11f1, either 54 or 51 pins are available for general-purpose i/o, depending on the package. these pins are arranged into ports a, b, c, d, e, f, and g. on the mc68hc11fc0, either 52 or 49 pins are available, depending on the package. i/o functions on some ports (b, c, f, and g) are affected by the mode of operation selected. in the sin- gle-chip and bootstrap modes, they are configured as parallel i/o data ports. in expanded and test modes, they are configured as follows: ?ports b and f are configured as the address bus. ?port c is configured as the data bus. ?port g bit 7 is configured as the optional program chip select cspr og . in addition, in expanded and test modes the r/w signal is configured as data bus direction control. the remaining ports (a, d, and e) are unaffected by mode changes. 7.1 port a port a is an eight-bit general-purpose i/o port (pa[7:0]) with a data register (porta) and a data direc- tion register (ddra). port a pins are available for shared use among the main timer, pulse accumulator, and general i/o functions, regardless of mode. four pins can be used for timer output compare func- tions (oc), three for input capture (ic), and one as either a fourth ic or a fifth oc. 7.2 port b port b is an eight-bit general-purpose output-only port in single-chip modes. in expanded modes, port b pins act as high-order address lines addr[15:8], and accesses to portb (the port b data register) are mapped externally. 7.3 port c port c is an eight-bit general-purpose i/o port with a data register (portc) and a data direction register (ddrc). in single-chip modes, port c pins are general-purpose i/o pins pc[7:0]. port c can be config- ured for wired-or operation in single-chip modes by setting the cwom bit in the opt2 register. in ex- panded modes, port c is the data bus data[7:0], and accesses to portc (the port c data register) are mapped externally. 7.4 port d port d is a six-bit general-purpose i/o port with a data register (portd) and a data direction register (ddrd). in all modes, the six port d lines (pd[5:0]) can be used for general-purpose i/o or for the serial communications interface (sci) or serial peripheral interface (spi) subsystems. port d can also be con- figured for wired-or operation. 7.5 port e port e is an eight-bit input-only port that is also used (on the mc68hc11f1 only) as the analog input port for the analog-to-digital converter. port e pins that are not used for the a/d system can be used as general-purpose inputs. however, porte should not be read during the sample portion of an a/d con- version sequence. note pe7 and pe0 are not available on the 80-pin mc68hc11fc0. pe7, pe4, and pe0 are not available on the 64-pin mc68hc11fc0. 7.6 port f port f is an eight-bit output-only port. in single-chip mode, port f pins are general-purpose output pins pf[7:0]. in expanded mode, port f pins act as low-order address outputs addr[7:0].
motorola mc68hc11f1/fc0 34 MC68HC11FTS/d 7.7 port g port g is an eight-bit general-purpose i/o port with a data register (portg) and a data direction register (ddrg). when enabled, the upper four lines (pg[7:4] can be used as chip-select outputs in expanded modes. when any of these pins are not being used for chip selects, they can be used for general-pur- pose i/o. port g can be configured for wired-or operation by setting the gwom bit in the opt2 reg- ister. note pg[1:0] are not available on the 64-pin mc68hc11fc0. 7.8 parallel i/o registers port pin function is mode dependent. do not confuse pin function with the electrical state of the pin at reset. port pins are either driven to a specified logic level or are configured as high impedance inputs. i/o pins configured as high-impedance inputs have port data that is indeterminate. the contents of the corresponding latches are dependent upon the electrical state of the pins during reset. in port descrip- tions, an ??indicates this condition. port pins that are driven to a known logic level during reset are shown with a value of either one or zero. some control bits are unaffected by reset. reset states for these bits are indicated with a ?? i = indeterminate value for ddrx bits, 0 = input and 1 = output. *these bits are not present on the 64-pin qfp version of the mc68hc11fc0. i = indeterminate value porta ? port a data register $x000 bit 7 6 5 4 3 2 1 bit 0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: i i i i i i i i alternate function: pai oc2 oc3 oc4 oc5/ic4 ic1 ic2 ic3 and/or: oc1 oc1 oc1 oc1 oc1 ? ? ? ddra ? port a data direction register $x001 bit 7 654321 bit 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 reset: 00000000 portg ? port g data register $x002 bit 7 6 5 4 3 2 1 bit 0 pg7 pg6 pg5 pg4 pg3 pg2 pg1* pg0* reset: i i i i i i i i alternate function: csprog csgen csio1 csio2
mc68hc11f1/fc0 motorola MC68HC11FTS/d 35 * following reset in expanded and test modes, pg7/csprg is configured as a program chip select, forcing the pin to be an output pin, even though the value of the ddg7 bit remains zero. for ddrx bits, 0 = input and 1 = output. the reset state of port b is mode dependent. in single-chip or bootstrap modes, port b pins are general- purpose outputs. in expanded and test modes, port b pins are high-order address outputs and portb is not in the memory map. the reset state of port f is mode dependent. in single-chip or bootstrap modes, port f pins are general- purpose outputs. in expanded and test modes, port f pins are low-order address outputs and portf is not in the memory map. the reset state of port c is mode dependent. in single-chip and bootstrap modes, port c pins are high- impedance inputs. in expanded or test modes, port c pins are data bus inputs/outputs and portc is not in the memory map. the r/w signal is used to control the direction of data transfers. for ddrx bits, 0 = input and 1 = output. ddrg ? port g data direction register $x003 bit 7 6 5 4 3 2 1 bit 0 ddg7* ddg6 ddg5 ddg4 ddg3 ddg2 ddg1 ddg0 reset: 0 0 0 0 0 0 0 0 portb ? port b data register $x004 bit 7 6 5 4 3 2 1 bit 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: 0 0 0 0 0 0 0 0 alternate function: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 portf ? port f data register $x005 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: 00000000 alternate function: addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 portc ? port c data register $x006 bit 7 654321 bit 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: iiiiiiii alternate function: data7 data6 data5 data4 data3 data2 data1 data0 ddrc ? port c data direction register $x007 bit 7 654321 bit 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 reset: 00000000
motorola mc68hc11f1/fc0 36 MC68HC11FTS/d for ddrx bits, 0 = input and 1 = output. note when the spi system is in slave mode, ddd5 has no meaning or effect. when the spi system is in master mode, ddd5 determines whether bit 5 of portd is an er- ror detect input (ddd5 = 0) or a general-purpose output (ddd5 = 1). if the spi sys- tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will be inputs regardless of the state of the associated ddr bits. if one or more of bits [4:2] are expected to be outputs, those bits will be outputs only if the associated ddr bits are set. u = unaffected by rest. porte is an input-only register. reads return the digital state of the i/o pins, and writes have no effect. on the mc68hc11f1, port e is shared with the analog-to-digital converter. (the a/d converter is not present on the mc68hc11fc0.) gwom port g wired-or mode option this bit affects all port g pins together. 0 = port g outputs are normal cmos outputs 1 = port g outputs act as open-drain outputs notes: 1. these bits are not present on the mc68hc11fc0 and will always read zero. 2. this bit is not present on the 64-pin qfp version of the mc68hc11fc0 and will always read zero. portd ? port d data register $x008 bit 7 654321 bit 0 0 0 pd5 pd4 pd3 pd2 pd1 pd0 reset: 0 0 iiiiii alternate function: ? ? ss sck mosi miso txd rxd ddrd ? port d data direction register $x009 bit 7 654321 bit 0 0 0 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 reset: 00000000 porte ? port e data $x00a bit 7 654321 bit 0 pe7 1 pe6 pe5 pe4 2 pe3 pe2 pe1 pe0 1 reset: uuuuuuuu alternate function an7 an6 an5 an4 an3 an2 an1 an0 opt2 ? system configuration option register 2 $x038 bit 7 6 5 4 3 2 1 bit 0 gwom cwom clk4x lirdv sprbyp reset 0 0 1 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 37 cwom ?port c wired-or mode option this bit affects all port c pins together. 0 = port c outputs are normal cmos outputs 1 = port c outputs act as open-drain outputs clk4x ?4xclk output enable refer to 4.3 system initialization registers , page 23 lirdv ?load instruction register driven refer to 4.3 system initialization registers , page 23 bits 3, 1, 0 ?not implemented. reads always return zero and writes have no effect. sprbyp refer to 10.2 spi registers , page 52.
motorola mc68hc11f1/fc0 38 MC68HC11FTS/d 8 chip-selects chip selects eliminate the need for additional external components to interface with peripherals in ex- panded non-multiplexed modes. chip-select registers control polarity, address block size, base ad- dress, and clock stretching. 8.1 chip-select operation there are four programmable chip selects on the mc68hc11f1 and mc68hc11fc0: two for external i/o (csio1 and csio2), one for external program space (cspr og ), and one general-purpose chip se- lect (csgen). cspr og is active low and becomes active at address valid time. cspr og is enabled by the pcsen bit of the chip-select control register (csctl). its address block size is selected by the psiza and psizb bits of csctl. use the i/o chip selects (csio1 and csio2) for external i/o devices. these chip-select addresses are found in the memory map block that contains the status and control registers. csio1 is mapped from $x060 to $x7ff, and csio2 is mapped from $x800 to $xfff, where x represents the reg[3:0] bits of the init register on the mc68hc11f1 or the reg[1:0] bits of the init register on the mc68hc11fc0. polarity and enable-disable selections are controlled by csctl register bits io1en, io1pl, io2en, and io2pl. the io1av and io2av bits of the csgsiz register determine whether the chip selects are valid during address or e-clock valid times. the general-purpose chip select is the most flexible of the four chip selects. polarity, valid assertion time, and block size are determined by the gnpol, gavld, gsiza, gsizb, and gsizc bits of the csgsiz register. the starting address is selected with the csgadr register. each of the four chip selects has two associated bits in the chip-select clock stretch register (csstrh). these bits allow clock stretching from zero to three cycles (full e-clock periods) to accommodate slow device interfaces. any of the chip selects can be programmed to cause a clock stretch to occur only during access to addresses that fall within that particular chip select? address range. during the stretch period, the e-clock is held high and the bus remains in the state that it is normally in at the end of e high time. internally, the clocks continue to run, which maintains the integrity of the timers and baud-rate generators. priority levels are assigned to prevent the four chip selects from conflicting with each other or with in- ternal memory and registers. there are two sets of priorities controlled by the value of the general-pur- pose chip-select priority bit (gcspr) of the csctl register. refer to table 17 . 8.2 chip-select registers io1sa, ios1b ?i/o chip-select 1 clock stretch io2sa, io2sb ?i/o chip-select 2 clock stretch gstha, gsthb ?general-purpose chip-select clock stretch pstha, pssthb ?program chip-select clock stretch each pair of bits selects the number of clock cycles of stretch for the corresponding chip select. csstrh ? clock stretching $x05c bit 7 6 5 4 3 2 1 bit 0 io1sa io1sb io2sa io2sb gstha gsthb pstha psthb reset: 0 0 0 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 39 * pcsen is set out of reset in expanded modes and cleared in single-chip modes. io1en ?i/o chip-select 1 enable 0 = csio1 disabled 1 = csio1 enabled io1pl ?i/o chip-select 1 polarity 0 = csio1 active low 1 = csio1 active high io1en ?i/o chip-select 2 enable 0 = csio2 disabled 1 = csio2 enabled io2pl ?i/o chip-select 2 polarity 0 = csio2 active low 1 = csio2 active high gcspr ?general-purpose chip-select priority 0 = program chip-select has priority over general-purpose chip-select 1 = general-purpose chip-select has priority over program chip-select refer to table 17 . notes: 1. eeprom is present on the mc68hc11f1 only. table 16 chip select clock stretch control clock stretch bits a, b clock stretch 0 0 0 cycles 0 1 1 cycle 1 0 2 cycles 1 1 3 cycles csctl ? chip-select control $x05d bit 7 6 5 4 3 2 1 bit 0 io1en io1pl io2en io2pl gcspr pcsen* psiza psizb reset: 0 0 0 0 0 0 0 table 17 chip select priorities gcspr = 0 gcspr = 1 on-chip registers on-chip registers on-chip ram on-chip ram bootloader rom bootloader rom on-chip eeprom 1 on-chip eeprom 1 i/o chip selects i/o chip selects program chip select general-purpose chip select general-purpose chip select program chip select
motorola mc68hc11f1/fc0 40 MC68HC11FTS/d pcsen ?program chip-select enable reset clears pcsen in single-chip modes and sets pcsen in expanded modes. 0 = csprog disabled 1 = csprog enabled psiza, psizb select size of program chip-select ga[15:10] ?general-purpose chip-select starting address these bits determine the starting address of the csgen valid address space and correspond to the high-order address bits addr[15:10]. table 19 illustrates how the block size selected determines which of this register's bits are valid. bits [1:0] ?not implemented. reads always return zero and writes have no effect. io1av ?i/o chip-select 1 address valid 0 = csio1 is valid during e-clock valid time (e-clock high) 1 = csio1 is valid during address valid time io2av ?i/o chip-select 2 address valid 0 = csio2 is valid during e-clock valid time (e-clock high) 1 = csio2 is valid during address valid time table 18 program chip select size control psiza psizb size address range 0 0 64 kbytes $0000?ffff 0 1 32 kbytes $8000?ffff 1 0 16 kbytes $c000?ffff 1 1 8 kbytes $e000?ffff csgadr ? general-purpose chip-select address register $x05e bit 7 6 5 4 3 2 1 bit 0 ga15 ga14 ga13 ga12 ga11 ga10 reset: 0 0 0 0 0 0 0 0 table 19 general purpose chip select starting address csgen block size csgadr bits valid 0 kbytes none 1 kbyte ga15 ?ga10 2 kbytes ga15 ?ga11 4 kbytes ga15 ?ga12 8 kbytes ga15 ?ga13 16 kbytes ga15 ?ga14 32 kbytes ga15 64 kbytes none csgsiz ? general-purpose chip-select size register $x05f bit 7 6 5 4 3 2 1 bit 0 io1av io2av gnpol gavld gsiza gsizb gsizc reset: 0 0 0 0 0 1 1 1
mc68hc11f1/fc0 motorola MC68HC11FTS/d 41 bit 5 ?not implemented. reads always return zero and writes have no effect. gnpol ?general-purpose chip-select polarity 0 = csgen is active low 1 = csgen is active high gavld ?general-purpose chip-select address valid 0 = csgen is valid during e-clock valid time (e-clock high) 1 = csgen is valid during address valid time gsiz[a:c] ?block size for csgen refer to table 20 for bit values. table 20 general-purpose chip select size control gsiz[a:c] address size 000 64 kbytes 001 32 kbytes 010 16 kbytes 011 8 kbytes 100 4 kbytes 101 2 kbytes 110 1 kbyte 111 0 kbytes (disabled)
motorola mc68hc11f1/fc0 42 MC68HC11FTS/d 9 serial communications interface (sci) the sci, a universal asynchronous receiver transmitter (uart) serial communications interface, is one of two independent serial i/o subsystems in the mc68hc11f1 and mc68hc11fc0. the sci has a standard non-return to zero (nrz) format (one start bit, eight or nine data bits, and one stop bit) and several selectable baud rates. the transmitter and receiver are independent but use the same data for- mat and bit rate. 9.1 sci block diagrams figure 9 sci transmitter block diagram tc tdre scsr1 sci status 1 sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx quests sci interrupt request internal data bus pin buffer and control h 10 (11) - bit tx shift register ddd1 scdr tx buffer transfer tx buffer shift enable jam enable preamble?am 1s break?am 0s (write only) force pin direction (out) size 8/9 m sccr1 sci control 1 transmitter baud rate clock tie tcie te sbk (8)76543210l pd1 txd t8 r8 wake rdrf idle or nf fe rie ilie re rwu
mc68hc11f1/fc0 motorola MC68HC11FTS/d 43 figure 10 sci receiver block diagram scsr1 sci status 1 sccr2 sci control 2 sci tx requests sci interrupt request internal data bus h 10 (11) - bit m sccr1 sci control 1 receiver baud rate clock rie ilie 8 7 6 5 4 3 2 1 0 l pd0 rxd scdr rx buffer rx shift register ddd0 pin buffer and control data recovery ? 16 stop start msb all ones re wakeup logic rdrf idle or nf fe rwu disable driver wake (read only) rdrf rie idle ilie or rie r8 t8 tdre re tc tie tcie te sbk
motorola mc68hc11f1/fc0 44 MC68HC11FTS/d 9.2 sci registers tclr ?clear baud rate counters (test) bit 6 ?not implemented. reads always return zero and writes have no effect. rckb ?sci baud-rate clock check (test) scp[2:0] ?sci baud rate prescaler selects these bits determine the baud rate prescaler frequency. refer to table 21 and figure 11 . scr[2:0] ?sci baud rate selects these bits determine the receiver and transmitter baud rate. refer to table 22 and figure 11 . the prescaler bits scp[2:0] determine the highest baud rate, and the scr[2:0] bits select an additional binary submultiple (divide by 1, 2, 4,..., through 128) of this highest baud rate. the result of these two dividers in series is the 16x receiver baud rate clock. the scr[2:0] bits are not affected by reset and can be changed at any time. they should not be changed, however, when an sci transfer is in progress. notes: 1. a blank table cell indicates that an uncommon rate results. baud ? baud rate $x02b bit 7 6 5 4 3 2 1 bit 0 tclr scp2 scp1 scp0 rckb scr2 scr1 scr0 reset: 0 0 0 0 0 u u u table 21 baud rate prescaler selection scp[2:0] divide internal clock by prescaler output 1 xtal = 4.0 mhz xtal = 4.9152 mhz xtal = 8.0 mhz xtal = 10.0 mhz xtal = 12.0 mhz xtal = 16.0 mhz xtal = 20.0 mhz xtal = 24.0 mhz x00 1 62500 76800 125000 156250 187500 250000 312500 375000 001 3 20833 25600 41667 52083 62500 83333 104167 125000 x10 4 15625 19200 31250 38400 46875 62500 76800 93750 x11 13 4800 5908 9600 12019 14423 19200 24038 28846 101 9 20830 table 22 baud rate selection scr[2:0] divide prescaler by baud rate prescaler output = 4800 prescaler output = 9600 prescaler output = 19200 prescaler output = 38400 prescaler output = 76800 0 0 0 1 4800 9600 19200 38400 76800 0 0 1 2 2400 4800 9600 19200 38400 0 1 0 4 1200 2400 4800 9600 19200 0 1 1 8 600 1200 2400 4800 9600 1 0 0 16 300 600 1200 2400 4800 1 0 1 32 150 300 600 1200 2400 1 1 0 64 75 150 300 600 1200 1 1 1 128 75 150 300 600
mc68hc11f1/fc0 motorola MC68HC11FTS/d 45 figure 11 illustrates the sci baud rate timing chain. the prescaler select bits determine the highest baud rate. the rate select bits determine additional divide-by-two stages to arrive at the receiver timing (rt) clock rate. the baud rate clock is the result of dividing the rt clock by 16. figure 11 sci baud rate generator block diagram oscillator and clock generator ( ? 4) xtal extal e internal bus clock (ph2) scr[2:0] ? 3 x00 001 ? 4 x10 ? 13 x11 0:0:0 ? 2 0:0:1 ? 2 0:1:0 ? 2 0:1:1 ? 2 1:0:1 ? 2 1:0:0 ? 2 1:1:1 ? 2 1:1:0 ? 16 sci receive baud rate (16x) sci transmit baud rate (1x) ? 9 101
motorola mc68hc11f1/fc0 46 MC68HC11FTS/d u = unaffected by reset r8 ?receive data bit 8 if m is set, r8 stores the ninth bit of the receive data character. t8 ?transmit data bit 8 if m is set, t8 stores the ninth bit of the transmit data character. bit 5 ?not implemented. reads always return zero and writes have no effect. m ?mode (select character format) 0 = 1 start bit, 8 data bits, 1 stop bit 1 = 1 start bit, 9 data bits, 1 stop bit wake ?wake up by address mark/idle 0 = wake up by idle line recognition 1 = wake up by address mark bits [2:0] ?not implemented. reads always return zero and writes have no effect. tie ?transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when the tdre flag is set tcie ?transmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when the tc flag is set rie ?receiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when the rdrf flag or the or flag is set ilie ?idle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ?transmitter enable when te goes from zero to one, one unit of idle character time (logic one) is queued as a preamble. 0 = transmitter disabled 1 = transmitter enabled re ?receiver enable 0 = receiver disabled 1 = receiver enabled sccr1 ? sci control register 1 $x02c bit 7 6 5 4 3 2 1 bit 0 r8 t8 0 m wake 0 0 0 reset: u u 0 0 0 0 0 0 sccr2 ? sci control register 2 $x02d bit 7 6 5 4 3 2 1 bit 0 tie tcie rie ilie te re rwu sbk reset: 0 0 0 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 47 rwu ?receiver wake up control 0 = normal sci receiver 1 = wake up enabled and receiver interrupt inhibited sbk ?send break 0 = break generator off 1 = break codes generated as long as sbk = 1 tdre ?transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr with tdre set and then writing to scdr. 0 = scdr is busy 1 = scdr is empty tc ?transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr with tc set and then writing to scdr. 0 = transmitter is busy 1 = transmitter is idle rdrf ?receive data register full flag this flag is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr with rdrf set and then reading scdr. 0 = scdr empty 1 = scdr full idle ?idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr with idle set and then reading scdr. 0 = rxd line is active 1 = rxd line is idle or ?overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear or by reading scsr with or set and then reading scdr. 0 = no overrun detected 1 = overrun detected nf ?noise error flag nf is set if majority sample logic detects anything other than a unanimous decision. clear nf by reading scsr with nf set and then reading scdr. 0 = unanimous decision 1 = noise detected fe ?framing error fe is set when a zero is detected where a stop bit was expected. clear the fe flag by reading scsr with fe set and then reading scdr. 0 = stop bit detected 1 = zero detected scsr ? sci status register $x02e bit 7 6 5 4 3 2 1 bit 0 tdre tc rdrf idle or nf fe 0 reset: 1 1 0 0 0 0 0 0
motorola mc68hc11f1/fc0 48 MC68HC11FTS/d bit 0 ?not implemented. reads always return zero and writes have no effect. i = indeterminate value reading scdr retrieves the last byte received in the receive data buffer. writing to scdr loads the transmit data buffer with the next byte to be transmitted. scdr ? serial communications data register $x02f bit 7 6 5 4 3 2 1 bit 0 bit 7 6 5 4 3 2 2 bit 0 reset: i i i i i i i i
mc68hc11f1/fc0 motorola MC68HC11FTS/d 49 10 serial peripheral interface the serial peripheral interface (spi) allows the mcu to communicate synchronously with peripheral de- vices and other microprocessors. the spi protocol facilitates rapid exchange of serial data between de- vices in a control system. the mc68hc11f1 and mc68hc11fc0 can be set up for master or slave operation. standard data rates can be as high as one half of the e-clock rate when configured as mas- ter, and as fast as the e-clock when configured as slave. the mc68hc11fc0 has an additional control bit that allows the spi baud rate counter to be bypassed. this allows a master mode baud rate equal to the e-clock frequency. 10.1 spi block diagram figure 12 spi block diagram system configuration option 2 register internal mcu clock ? 2 ? 4 ? 16 ? 32 divider select sprbyp spi control register spie spe dwom mstr cpha dotted line connections 8-bit shift register read data buffer msb lsb clock m m s s miso pd2 mosi pd3 m s sck pd4 clock logic ss pd5 spr1 pin control logic cpol spr0 spif wcol modf spi status register spr0 spr1 mstr cpha cpol spie spe mstr spi control modf wcol spif spe dwom mstr present on mc68hc11fc0 only internal data bus spi interrupt request
motorola mc68hc11f1/fc0 50 MC68HC11FTS/d 10.2 spi registers u = unaffected by reset spie ?spi interrupt enable when spi interrupts are enabled, a hardware interrupt sequence is requested each time the spif or modf status flag is set. spi interrupts are inhibited if this bit is cleared or if the i bit in the condition code register is one. 0 = spi interrupt disabled 1 = spi interrupt enabled spe ?spi enable when the spe bit is set, pd[5:2] are dedicated to the spi function. if the spi is in master mode and the ddrd bit 5 is set, then pd5/ss becomes a general-purpose output instead of the ss input. 0 = spi off 1 = spi on dwom ?port d wired-or mode option for spi pins pd[5:2] 0 = normal cmos outputs 1 = open-drain outputs mstr ?master mode select 0 = slave mode 1 = master mode cpol clock polarity when the clock polarity bit is cleared and data is not being transferred, the sck pin of the master device has a steady state low value. when cpol is set, sck idles high. refer to figure 13 . cpha clock phase the clock phase bit, in conjunction with the cpol bit, controls the clock-data relationship between mas- ter and slave. the cpha bit selects one of two clocking protocols. refer to figure 13 . figure 13 spi data clock timing diagram spcr ? spi control register $x028 bit 7 6 5 4 3 2 1 bit 0 spie spe dwom mstr cpol cpha spr1 spr0 reset: 0 0 0 0 0 1 u u sck cycle # (for reference) 12345678 sck (cpol = 0) sck (cpol = 1) (cpha = 0) data out (cpha = 1) data out ss (to slave) sample input sample input msb654321lsb msb654321lsb
mc68hc11f1/fc0 motorola MC68HC11FTS/d 51 spr[1:0] ?spi clock rate selects these two bits select the spi clock (sck) rate when the device is configured as a master. when the device is configured as a slave, the bits have no effect. refer to table 23 . note the sprbyp bit in opt2 on the mc68hc11fc0 allows the spi baud rate counter to be bypassed. this permits a maximum master mode baud rate equal to the e- clock frequency on the mc68hc11fc0. sprbyp is not present on the mc68hc11f1 . spif ?spi transfer complete flag spif is set when an spi transfer is complete. it is cleared by reading spsr with spif set, followed by a read or write of spdr. wcol ?write collision wcol is set when spdr is written while a transfer is in progress. it is cleared by reading spsr with wcol set, followed by a read or write of spdr. 0 = no write collision 1 = write collision bit 5 ?not implemented. reads always return zero and writes have no effect. modf ?mode fault a mode fault terminates spi operation. set when ss is pulled low while mstr = 1. modf is cleared by reading spsr read with modf set, followed by a write to spcr. 0 = no mode fault 1 = mode fault bits [3:0] ?not implemented. reads always return zero and writes have no effect. incoming spi data is double buffered. outgoing spi data is single buffered. table 23 spi baud rates input frequency spr[1:0] = 00 spr[1:0] = 01 spr[1:0] = 10 spr[1:0] = 11 1 mhz 500 kbps 250 kbps 62.5 kbps 31.25 kbps 2 mhz 1 mbps 500 kbps 125 kbps 62.5 kbps 3 mhz 1.5 mbps 750 kbps 187.5 kbps 93.75 kbps 4 mhz 2 mbps 1 mbps 250 kbps 125 kbps 5 mhz 2.5 mbps 1.25 mbps 312.5 kbps 156.25 kbps 6 mhz 3 mbps 1.5 mbps 375 kbps 187.5 kbps any e e/2 e/4 e/16 e/32 spsr ? spi status register $x029 bit 7 6 5 4 3 2 1 bit 0 spif wcol 0 modf 0 0 0 0 reset: 0 0 0 0 0 0 0 0 spdr ? spi data register $x02a bit 7 6 5 4 3 2 1 bit 0 bit 7 6 5 4 3 2 1 bit 0
motorola mc68hc11f1/fc0 52 MC68HC11FTS/d bits [7:4] ?see 4.3 system initialization registers , page 22. bits 3, 1, 0 ?not implemented. reads always return zero and writes have no effect. sprbyp ?spi baud rate counter bypass 0 = enable spi baud rate counter 1 = bypass spi baud rate counter when the spi baud rate counter is bypassed, the spi can transmit at a maximum master mode baud rate equal to the e-clock frequency. sprbyp is present only on the mc68hc11fc0 and overrides the setting of spr[1:0] in spcr . opt2 ? system configuration option register 2 $x038 bit 7 6 5 4 3 2 1 bit 0 gwom cwom clk4x lirdv sprbyp reset 0 0 1 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 53 11 analog-to-digital converter the mc68hc11f1 analog-to-digital (a/d) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. the a/d system is an 8-channel, 8-bit, multiplexed- input, successive-approximation converter, accurate to 1 least significant bit (lsb). because the ca- pacitive charge redistribution technique used includes a built-in sample-and-hold, no external sample- and-hold is required. dedicated lines v rh and v rl provide the reference supply voltage inputs. systems operating at clock rates of 750 khz or below must use an internal rc oscillator. the csel bit in the option register se- lects the clock source for the a/d system. (the csel bit is described in 11.3 a/d registers , page 56.) a multiplexer allows the single a/d converter to select one of 16 analog signals, as shown in table 24 . note the a/d converter is present on the mc68hc11f1 only . figure 14 a/d converter block diagram ea9 a/d block pe0 an0 pe1 an1 pe2 an2 pe3 an3 pe4 an4 pe5 an5 pe6 an6 pe7 an7 analog mux 8-bit capacitive dac with sample and hold successive approximation register and control adctl a/d control cb cc cd mult scan ccf ca adr1 a/d result 1 adr2 a/d result 2 adr3 a/d result 3 adr4 a/d result 4 result register interface result internal data bus v rh v rl
motorola mc68hc11f1/fc0 54 MC68HC11FTS/d 11.1 input pins port e pins can also be used as digital inputs. reads of port e pins are not recommended during the sample portion of an a/d conversion cycle, when the gate signal to the n-channel input gate is on. be- cause no p-channel devices are directly connected to either input pins or reference voltage pins, volt- ages above v dd do not cause a latchup problem, although current should be limited according to maximum ratings. figure 15 is a functional diagram of an input pin. figure 15 electrical model of an analog input pin (sample mode) 11.2 conversion sequence a/d converter operations are performed in sequences of four conversions each. a conversion sequence can be repeated continuously or stop after one iteration. the conversion complete flag (ccf) is set after the fourth conversion in a sequence to show the availability of data in the result registers. figure 16 shows the timing of a typical sequence. synchronization is referenced to the system e clock. figure 16 a/d conversion sequence diffusion/poly < 2 pf coupler 400 na junction leakage + ~20v ?~0.7v * * this analog switch is closed only during the 12-cycle sample time. v rl input + ~12v ?~0.7v protection device 4 k w dummy n-channel output device analog input pin ~ 20 pf dac capacitance 0 32 64 96 128 ?e cycles sample analog input successive approximation sequence msb 4 cycles bit 6 2 cyc bit 5 2 cyc bit 4 2 cyc bit 3 2 cyc bit 2 2 cyc bit 1 2 cyc lsb 2 cyc 2 cyc end repeat sequence, scan = 1 set cc flag convert first channel, update adr1 convert second channel, update adr2 convert third channel, update adr3 convert fourth channel, update adr4 12 e cycles write to adctl e clock
mc68hc11f1/fc0 motorola MC68HC11FTS/d 55 11.3 a/d registers i = indeterminate value ccf ?conversions complete flag a read-only status indicator, this bit is set when all four a/d result registers contain valid conversion re- sults. each time the adctl register is overwritten, this bit is automatically cleared to zero and a con- version sequence is started. in the continuous mode, ccf is set at the end of the first conversion sequence. bit 6 ?not implemented. reads always return zero and writes have no effect. scan ?continuous scan control 0 = do four conversions and stop 1 = convert four channels in selected group continuously mult ?multiple channel/single channel control 0 = convert single channel selected 1 = convert four channels in selected group cd?a ?channel select d through a refer to table 24 . when a multiple channel mode is selected (mult = 1), the two least significant chan- nel select bits (cb and ca) have no meaning and the cd and cc bits specify which group of four chan- nels is to be converted. notes: 1. used for factory testing. adctl ? a/d control/status $x 030 bit 7 6 5 4 3 2 1 bit 0 ccf 0 scan mult cd cc cb ca reset: i 0 i i i i i i table 24 a/d converter channel assignments channel select control bits cd:cc:cb:ca channel signal result in adrx if mult = 1 0000 an0 adr1 0001 an1 adr2 0010 an2 adr3 0011 an3 adr4 0100 an4 adr1 0101 an5 adr2 0110 an6 adr3 0111 an7 adr4 10xx reserved adr1?dr4 1100 v rh 1 adr1 1101 v rl 1 adr2 1110 (v rh )/2 1 adr3 1111 reserved 1 adr4
motorola mc68hc11f1/fc0 56 MC68HC11FTS/d each read-only result register holds an eight-bit conversion result. writes to these registers have no ef- fect. data in the a/d converter result registers is valid when the ccf flag in the adctl register is set, indicating a conversion sequence is complete. if conversion results are needed sooner, refer to figure 16 , which shows the a/d conversion sequence diagram. *can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes. adpu ?a/d power up 0 = a/d powered down 1 = a/d powered up csel ? clock select 0 = a/d and eeprom use system e-clock 1 = a/d and eeprom use internal rc clock bits [5:0] ?refer to 4.3 system initialization registers , page 23. notes: 1. % of v rh ? rl 2. volts for v rl = 0; v rh = 5.0 v adr1 ?adr4 ? a/d results $x031 ?$x034 $x031 bit 7 654321 bit 0 adr1 $x032 bit 7 654321 bit 0 adr2 $x033 bit 7 654321 bit 0 adr3 $x034 bit 7 654321 bit 0 adr4 table 25 analog input to 8-bit result translation table bit 7 654321 bit 0 percentage 1 50% 25% 12.5% 6.25% 3.12% 1.56% 0.78% 0.39% volts 2 2.500 1.250 0.625 0.3125 0.1562 0.0781 0.0391 0.0195 option ? system configuration options $x039 bit 7 6 5 4 3 2 1 bit 0 adpu csel irqe* dly* cme fcme* cr1* cr0* reset: 0 0 0 1 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 57 12 main timer the main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. the timer drives the three input capture (ic) channels, four output compare (oc) channels, one channel pro- grammable for either ic or oc, and the pulse accumulator (pa). all of these functions share port a. the main timer also drives the pulse accumulator, real-time interrupt (rti), and computer operating properly (cop) watchdog circuits. 12.1 timer operation the following tables summarize timing periods for various m68hc11 functions derived from the main timer for several crystal frequencies. table 26 timer subsystem count and overflow periods e-clock frequency pr[1:0] = 00 pr[1:0] = 01 pr[1:0] = 10 pr[1:0] = 11 1 count tcnt overflow 1 count tcnt overflow 1 count tcnt overflow 1 count tcnt overflow 1 mhz 1.000 m s 65.536 ms 4.000 m s 262.144 ms 8.000 m s 524.288 ms 16.000 m s 1.049 s 2 mhz 0.500 m s 32.768 ms 2.000 m s 131.072 ms 4.000 m s 262.144 ms 8.000 m s 524.288 ms 3 mhz 0.333 m s 21.845 ms 1.333 m s 87.381 ms 2.667 m s 174.763 ms 5.333 m s 349.525 ms 4 mhz 0.250 m s 16.384 ms 1.000 m s 65.536 ms 2.000 m s 131.072 ms 4.000 m s 262.144 ms 5 mhz 0.200 m s 13.107 ms 0.800 m s 52.429 ms 1.600 m s 104.858 ms 3.200 m s 209.715 ms 6 mhz 0.167 m s 10.923 ms 0.667 m s 43.691 ms 1.333 m s 87.381 ms 2.667 m s 174.763 ms any e 1/e 2 16 /e 4/e 2 18 /e 8/e 2 19 /e 16/e 2 20 /e table 27 real-time interrupt periods e-clock frequency rtr[1:0] = 00 rtr[1:0] = 01 rtr[1:0] = 10 rtr[1:0] = 11 1 mhz 8.192 ms 16.384 ms 32.768 ms 65.536 ms 2 mhz 4.096 ms 8.192 ms 16.384 ms 32.768 ms 3 mhz 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4 mhz 2.048 ms 4.096 ms 8.192 ms 16.384 ms 5 mhz 1.638 ms 3.277 ms 6.554 ms 13.107 ms 6 mhz 1.366 ms 2.731 ms 5.461 ms 10.923 ms any e 2 13 /e 2 14 /e 2 15 /e 2 21 /e table 28 cop watchdog time-out periods e-clock frequency rtr[1:0] = 00 rtr[1:0] = 01 rtr[1:0] = 10 rtr[1:0] = 11 1 mhz 32.768 ms 131.072 ms 524.288 ms 2.097 s 2 mhz 16.384 ms 65.536 ms 262.144 ms 1.049 s 3 mhz 10.923 ms 43.691 ms 174.763 ms 699.051 ms 4 mhz 8.192 ms 32.768 ms 131.072 ms 524.288 ms 5 mhz 6.554 ms 26.214 ms 104.858 ms 419.430 ms 6 mhz 5.461 ms 21.845 ms 87.381 ms 349.525 ms any e 2 15 /e 2 17 /e 2 19 /e 2 21 /e
motorola mc68hc11f1/fc0 58 MC68HC11FTS/d figure 17 main timer ic/oc block 16-bit latch clk port a pin tflg 1 status flags oc1f pa3 pa4 pa5 pa6 pa7 i4/o5 16-bit comparator = toc1 (lo) 16-bit free running counter tcnt (hi) tcnt (lo) toi pr1 16-bit timer bus oc5 ic4 tmsk 1 interrupt enables cforc pa0 pa1 pa2 ic3 ic2 ic1 pr0 e clock oc1 oc2/oc1 oc3/oc1 oc4/oc1 ic4/oc5 oc1 tof 8 foc1 toc1 (hi) oc3i oc4i i4o5i 7 6 5 4 foc2 foc3 foc4 foc5 16-bit comparator = toc2 (lo) toc2 (hi) 16-bit comparator = toc3 (lo) toc3 (hi) 16-bit comparator = toc4 (lo) toc4 (hi) 16-bit comparator = ti4o5 (lo) ti4o5 (hi) 3 2 1 ic1i ic2i ic3i oc1i oc2i oc2f oc3f oc4f i4o5f ic1f tic1 (lo) tic1 (hi) ic2f ic3f tic2 (lo) tic2 (hi) tic3 (lo) tic3 (hi) 9 prescaler divide by 1, 4, 8 or 16 interrupt requests bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 control (note 1) 16-bit latch clk 16-bit latch clk 16-bit latch clk to pulse accumulator port a pins note: registers that control port a action include ddra, oc1m, oc1d, pactl, tctl1 and tctl2.
mc68hc11f1/fc0 motorola MC68HC11FTS/d 59 12.2 timer registers focx ?force output compare x action 0 = not affected 1 = output compare x action occurs, but ocxf flag bit is not set bits [2:0] ?not implemented. reads always return zero and writes have no effect. bits set in oc1m allow oc1 to output the corresponding oc1d bits in port a when a successful com- pare event occurs. oc1m[7:3] ?output compare masks 0 = control of the corresponding port a pin is disabled 1 = control of the corresponding port a pin is enabled bits [2:0] ?not implemented. reads always return zero and writes have no effect. oc1d[7:3] ?output compare data data in oc1dx is output to port a bit x on successful oc1 compares if oc1mx is set. bits [2:0] ?not implemented. reads always return zero and writes have no effect. the 16-bit read-only tcnt register contains the prescaled value of the 16-bit timer. a full counter read addresses the most significant byte (msb) first. a read of this address causes the least significant byte to be latched into a buffer for the next cpu cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the msb read cycle. cforc timer force compare $x00b bit 7 6 5 4 3 2 1 bit 0 foc1 foc2 foc3 foc4 foc5 0 0 0 reset: 0 0 0 0 0 0 0 0 oc1m output compare 1 mask $x00c bit 7 6 5 4 3 2 1 bit 0 oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 reset: 0 0 0 0 0 0 0 0 oc1d output compare 1 data $x00d bit 7 6 5 4 3 2 1 bit 0 oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 reset: 0 0 0 0 0 0 0 0 tcnt timer count $x00e, $x00f $x00e bit 15 14 13 12 11 10 9 bit 8 high $x00f bit 7 6 5 4 3 2 1 bit 0 low reset: 0 0 0 0 0 0 0 0
motorola mc68hc11f1/fc0 60 MC68HC11FTS/d ticx registers are not affected by reset. all tocx register pairs are reset to ones ($ffff). ti4/o5 is reset to ones ($ffff). om2?m5 ?output mode ol2?l5 ? output level each omx?lx bit pair determines the output action taken on the corresponding ocx pin after a suc- cessful compare, as shown in table 29 . oc5 functions only if the i4/o5 bit in the pactl register is cleared. tic1?ic3 timer input capture $x010?x015 $x010 bit 15 14 13 12 11 10 9 bit 8 high $x011 bit 7 6 5 4 3 2 1 bit 0 low $x012 bit 15 14 13 12 11 10 9 bit 8 high $x013 bit 7 6 5 4 3 2 1 bit 0 low $x014 bit 15 14 13 12 11 10 9 bit 8 high $x015 bit 7 6 5 4 3 2 1 bit 0 low toc1?oc4 timer output compare $x016?x01d $x016 bit 15 14 13 12 11 10 9 bit 8 high $x017 bit 7 6 5 4 3 2 1 bit 0 low $x018 bit 15 14 13 12 11 10 9 bit 8 high $x019 bit 7 6 5 4 3 2 1 bit 0 low $x01a bit 15 14 13 12 11 10 9 bit 8 high $x01b bit 7 6 5 4 3 2 1 bit 0 low $x01c bit 15 14 13 12 11 10 9 bit 8 high $x01d bit 7 6 5 4 3 2 1 bit 0 low ti4/o5 timer input capture 4/output compare 5 $x01e, $x01f $x01e bit 15 14 13 12 11 10 9 bit 8 high $x01f bit 7 6 5 4 3 2 1 bit 0 low tctl1 timer control 1 $x020 bit 7 6 5 4 3 2 1 bit 0 om2 ol2 om3 ol3 om4 ol4 om5 ol5 reset: 0 0 0 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 61 edgxb, edgxa ?input capture edge control each edgxb, edgxa pair determines the polarity of the input signal on the corresponding icx that will trigger an input capture, as shown in table 30 . ic4 functions only if the i4/o5 bit in the pactl register is set. bits in tmsk1 correspond bit for bit with flag bits in tflg1. each bit that is set in tmsk1 enables the corresponding interrupt source. ocxi ?output compare x interrupt enable if the ocxi enable bit is set when the ocxf flag bit is set, a hardware interrupt sequence is requested. i4/o5i ?input capture 4/output compare 5 interrupt enable when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt enable bit. when i4/o5 in pactl is zero, i4/o5i is the output compare 5 interrupt enable bit. icxi ?input capture x interrupt enable if the icxi enable bit is set when the icxf flag bit is set, a hardware interrupt sequence is requested. bits in tflg1 are cleared by writing a one to the corresponding bit positions. table 29 output compare actions omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to zero 1 1 set ocx output line to one tctl2 timer control 2 $x021 bit 7 6 5 4 3 2 1 bit 0 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a reset: 0 0 0 0 0 0 0 0 table 30 input capture configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge tmsk1 timer interrupt mask 1 $x022 bit 7 6 5 4 3 2 1 bit 0 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i reset: 0 0 0 0 0 0 0 0 tflg1 ? timer interrupt flag 1 $x023 bit 7 6 5 4 3 2 1 bit 0 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f reset: 0 0 0 0 0 0 0 0
motorola mc68hc11f1/fc0 62 MC68HC11FTS/d ocxf ?output compare x flag set each time the counter matches output compare x value. i4/o5f ?input capture 4/output compare 5 flag set by ic4 or oc5, depending on which function was enabled by i4/o5 of pactl. icxf ? input capture x flag set each time a selected active edge is detected on the icx input line. bits [7:4] in tmsk2 correspond bit for bit with flag bits in tflg2. setting any of these bits enables the corresponding interrupt source. tmsk2 can be written only once in the first 64 cycles out of reset in normal modes, or at any time in special modes. toi ?timer overflow interrupt enable 0 = timer overflow interrupt disabled 1 = interrupt requested when tof is set rtii ?real-time interrupt enable 0 = real-time interrupt disabled 1 = interrupt requested when rtif is set bits [5:4] ?see 13.2 pulse accumulator registers , page 64. bits [3:2] ?not implemented. reads always return zero and writes have no effect. pr[1:0] ?timer prescaler select determines the main timer prescale factor as shown in table 31 . see table 26 for specific frequencies. bits in this register indicate when certain timer system events have occurred. coupled with the four high-order bits of tmsk2, the bits of tflg2 allow the timer subsystem to operate in either a polled or interrupt driven system. each bit of tflg2 corresponds to a bit in tmsk2 in the same position. bits in tflg2 are cleared by writing a one to the corresponding bit positions. tof ?timer overflow flag set when tcnt rolls over from $ffff to $0000. tmsk2 timer interrupt mask 2 $x024 bit 7 6 5 4 3 2 1 bit 0 toi rtii paovi paii 0 0 pr1 pr0 reset: 0 0 0 0 0 0 0 0 table 31 main timer prescale control pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16 tflg2 timer interrupt flag 2 $x025 bit 7 6 5 4 3 2 1 bit 0 tof rtif paovf paif 0000 reset: 0 0 0 0 0 0 0 0
mc68hc11f1/fc0 motorola MC68HC11FTS/d 63 rtif ?real-time interrupt flag set periodically at a rate based on bits rtr[1:0] in the pactl register. bits [5:4] ?see 13.2 pulse accumulator registers , page 65. bits [3:0] ?not implemented. reads always return zero and writes have no effect. bit 7 ?not implemented. reads always return zero and writes have no effect. bits [6:4] ?see 13.2 pulse accumulator registers , page 65. bit 3 ?not implemented. reads always return zero and writes have no effect. i4/o5 ?configure ti4/o5 register for ic or oc 0 = oc5 function enabled 1 = ic4 function enabled rtr[1:0] ?rti interrupt rate selects these two bits select one of four rates for the real-time interrupt circuit, as shown in table 32 . pactl pulse accumulator control $x026 bit 7 6 5 4 3 2 1 bit 0 0 paen pamod pedge 0 i4/o5 rtr1 rtr0 reset: 0 0 0 0 0 0 0 0 table 32 real-time interrupt periods e-clock frequency rtr [1:0] = %00 rtr [1:0] = 01 rtr [1:0] = 10 rtr [1:0] = 11 1 mhz 8.192 ms 16.384 ms 32.768 ms 65.536 ms 2 mhz 4.906 ms 8.192 ms 16.384 ms 32.768 ms 3 mhz 2.731 ms 5.461 ms 10.923 ms 21.845 ms 4 mhz 2.048 ms 4.096 ms 8.192 ms 16.384 ms 5 mhz 1.638 ms 3.277 ms 6.554 ms 13.107 ms 6 mhz 1.366 ms 2.731 ms 5.461 ms 10.923 ms any e 2 13 /e 2 14 /e 2 15 /e 2 16 /e
motorola mc68hc11f1/fc0 64 MC68HC11FTS/d 13 pulse accumulator the pulse accumulator can be used either to count events or measure the duration of a particular event. in event counting mode, the pulse accumulator? 8-bit counter increments each time a specified edge is detected on the pulse accumulator input pin, pa7. the maximum clocking rate for this mode is the e- clock divided by two. in gated time accumulation mode, an internal clock increments the 8-bit counter at a rate of e-clock ? 64 while the input at pa7 remains at a predetermined logic level. 13.1 pulse accumulator block diagram figure 18 pulse accumulator block diagram 13.2 pulse accumulator registers bits [7:4] in tmsk2 correspond bit for bit with flag bits in tflg2. setting any of these bits enables the corresponding interrupt source. tmsk2 ? timer interrupt mask 2 $x024 bit 7 6 5 4 3 2 1 bit 0 toi rtii paovi paii 0 0 pr1 pr0 reset: 0 0 0 0 0 0 0 0 pacnt 8-bit counter 2:1 mux pa7/ enable overflow 1 interrupt requests internal data bus input buffer & edge detection pactl tflg2 tmsk2 paovi paii paen pamod pedge paovf paif output buffer pai edge paen e ? 64 clock (from main timer) pai/oc1 from main timer oc1 paen 2 clock from status flags interrupt enables control ddra
mc68hc11f1/fc0 motorola MC68HC11FTS/d 65 bits[7:6] ?see 12.2 timer registers , page 62. paovi ?pulse accumulator overflow interrupt enable 0 = pulse accumulator overflow interrupt disabled 1 = interrupt requested when paovf in tflg2 is set paii ?pulse accumulator interrupt enable 0 = pulse accumulator interrupt disabled 1 = interrupt requested when paif in tflg2 is set bits [3:2] ?not implemented. reads always return zero and writes have no effect. bits [1:0] ?see 12.2 timer registers , page 62. bits in tflg2 are cleared by writing a one to the corresponding bit positions. bits [7:6] ?see 12.2 timer registers , page 62. paovf ?pulse accumulator overflow flag set when pacnt rolls over from $ff to $00 paif ?pulse accumulator input edge flag set each time a selected active edge is detected on the pai input line bits [3:0] ?not implemented. reads always return zero and writes have no effect. bit 7 ?not implemented. reads always return zero and writes have no effect. paen ?pulse accumulator system enable 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ?pulse accumulator mode 0 = event counter 1 = gated time accumulation pedge ?pulse accumulator edge control this bit has different meanings depending on the state of the pamod bit, as shown in table 33 . tflg2 ? timer interrupt flag 2 $x025 bit 7 6 5 4 3 2 1 bit 0 tof rtif paovf paif 0000 reset: 0 0 0 0 0 0 0 0 pactl ? pulse accumulator control $x026 bit 7 6 5 4 3 2 1 bit 0 0 paen pamod pedge 0 i4/o5 rtr1 rtr0 reset: 0 0 0 0 0 0 0 0
motorola mc68hc11f1/fc0 66 MC68HC11FTS/d bit 3 ?not implemented. reads always return zero and writes have no effect. bits [2:0] ?see 12.2 timer registers , page 63. u = unaffected by reset this eight-bit read/write register contains the count of external input events at the pai input, or the ac- cumulated count. the pacnt is readable even if pai is not active in gated time accumulation mode. the counter is not affected by reset and can be read or written at any time. counting is synchronized to the internal ph2 clock so that incrementing and reading occur during opposite half cycles. table 33 pulse accumulator edge control pamod pedge action on clock 0 0 pai falling edge increments the counter. 0 1 pai rising edge increments the counter. 1 0 a zero on pai inhibits counting. 1 1 a one on pai inhibits counting. pacnt ? pulse accumulator count $x027 bit 7 6 5 4 3 2 1 bit 0 bit 7 6 5 4 3 2 1 bit 0 reset: u u u u u u u u
mc68hc11f1/fc0 motorola MC68HC11FTS/d 67
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